IC设计教程

最后发表: 2008-9-6 15:33 by pzb19841116

主题:416, 帖数: 9450

synthesis教程 (今日: 1)

最后发表: 2008-9-7 08:10 by weiyongc

主题:429, 帖数: 4535

静态时序分析

最后发表: 2008-9-4 10:06 by renelving

主题:450, 帖数: 4129

DFT

最后发表: 2008-9-6 09:30 by 店小二

主题:571, 帖数: 3460

4765 1 ...‹‹7 8910 11 12 13 14 15 16 ››... 96

芯片综合

标题	作者	回复/查看	最后发表
lm336	figle 2008-6-10	0 / 11	2008-6-10 20:18 by figle
請問8bit的數x，做X mod 5 运算怎么做？	flyingthink 2008-6-10	2 / 25	2008-6-10 16:11 by victor_wang
how to deal with "clock used as data" issue?	swlin 2008-4-19	15 / 283	2008-6-10 14:20 by kuangjianghua
键盘控制状态机问题	figle 2008-6-9	2 / 15	2008-6-10 00:31 by lxy007
總線接口芯片的設計	fayindark 2008-6-8	0 / 23	2008-6-8 20:29 by fayindark
bbbbbbbbbbbbbbbbbbbbbbbbbbbbb	lala01 2008-6-8	0 / 19	2008-6-8 17:22 by lala01
DC综合时，如何根据设计规则抽象出时序约束和环境约束？？	3274196 2008-4-18	22 / 209	2008-6-8 16:55 by ethanpan
DC详细的中文资料 1 2	limingic 2008-4-12	51 / 424	2008-6-8 04:24 by feiyunliwang
一个问题的解决..	gubo1 2008-5-28	5 / 105	2008-6-7 12:11 by dianyubaobei
综合报错，内部的CLK using as "data"	老婆是GIGI 2008-5-24	3 / 95	2008-6-6 21:28 by eric77he
dc_教程（word版） 1 2	jeemy 2008-4-7	38 / 252	2008-6-6 17:35 by chaulee
如果给一个设计加约束？	COSMOSD 2008-5-22	10 / 136	2008-6-6 16:48 by xyy277184317
关于rtl代码和综合后网表之间的对应关系？	TomPaul 2008-5-22	18 / 216	2008-6-6 16:47 by xyy277184317
请问如何做clock balance？	frozen_king 2008-5-29	2 / 62	2008-6-6 16:45 by xyy277184317
如何设置模拟输入输出的约束	aoe 2008-6-3	5 / 45	2008-6-6 16:37 by xyy277184317
综合问题	hawkingy 2008-6-4	4 / 50	2008-6-6 16:36 by xyy277184317
请教个同步器约束的问题	qingchuyu 2008-6-3	4 / 70	2008-6-6 16:36 by xyy277184317
欢迎加入IT精英联盟QQ群：51937366	傻鹏 2008-5-29	2 / 23	2008-6-6 16:31 by xyy277184317
请教各位用ModelSim仿真DC网表时出现亚稳态如何解决	rqz102 2008-6-2	9 / 67	2008-6-6 16:31 by chaulee
Standard Delay File spec	snleo 2008-6-1	5 / 61	2008-6-6 16:31 by xyy277184317
flatten netlist 与 hierarchy netlist 的区别	lionking_2046 2008-5-29	6 / 126	2008-6-6 16:29 by xyy277184317
基于FPGA 的八位RISC CPU 的设计	huhongli 2008-5-31	5 / 48	2008-6-6 16:24 by xyy277184317
中兴ASIC设计资料 1 2	limingic 2008-4-12	47 / 405	2008-6-6 16:22 by xyy277184317
【转贴】	COSMOSD 2008-5-26	5 / 123	2008-6-6 16:21 by xyy277184317
定constraint的问题	sjtudegivenchy 2008-6-5	4 / 61	2008-6-6 16:03 by xyy277184317
请教	anserman 2008-6-4	2 / 24	2008-6-6 15:58 by xyy277184317
请问行波时钟的约束怎么加	nethunter 2008-6-4	2 / 40	2008-6-5 15:39 by nethunter
setup time 和hold time的练习题	stephen_0921 2008-4-7	14 / 294	2008-6-5 11:43 by 东方之子
link的作用到底是啥？	oceanyt 2008-5-29	2 / 126	2008-6-5 10:01 by stephen_0921
Synopsys Fans群: 13934768	reset_n 2008-5-7	6 / 50	2008-6-5 09:53 by mayrain
请教关于rst信号的removal time \recovery time 问题	peng_1983 2008-5-27	22 / 189	2008-6-5 09:01 by china_soc
dc后寄存器给优化掉	hawkingy 2008-6-3	7 / 97	2008-6-4 11:42 by ai520520
代码的综合问题	xjtu_zhanglei 2008-6-3	4 / 80	2008-6-4 10:00 by oceanyt
timing loop的问题	qifan 2008-6-2	4 / 70	2008-6-3 09:21 by victor_wang
DC 中如何为某条路径增加延时？	lww107 2008-6-2	4 / 80	2008-6-2 19:59 by yx.yang
关于DC综合出的组合路径的问题	zhengyudennis 2008-5-30	2 / 75	2008-6-2 17:46 by wangqi1012
单端口寄存器堆和单端口sram的面积相差几倍？	earthowen311 2008-5-30	1 / 40	2008-5-30 21:10 by qingchuyu
芯片手册!!!	zpbeyond 2008-5-30	4 / 26	2008-5-30 21:04 by sunboy6828
请教关于rst信号的removal time \recovery time 问题	peng_1983 2008-5-27	17 / 153	2008-5-30 20:56 by zhengyudennis
有没有用过这个片子的啊NB100LVEP224???求助!!!!!	tiebing007 2008-5-29	0 / 4	2008-5-29 23:15 by tiebing007
fv碰到的一个警告求助	TomPaul 2008-5-26	4 / 49	2008-5-29 16:54 by TomPaul
帮我看看这块芯片	figle 2008-5-19	3 / 71	2008-5-29 10:26 by figle
亚稳态问题，请进	ttsky001 2008-4-2	19 / 274	2008-5-29 10:14 by 新手上路学习中
关于timing loop问题	老婆是GIGI 2008-5-27	12 / 133	2008-5-28 21:25 by gwbing
请问芯片CP测试的流程	lhweiaiwf 2008-5-28	3 / 34	2008-5-28 20:44 by lwf0012468
IC设计中的IT环境 1 2	soway 2008-3-31	51 / 563	2008-5-28 12:54 by 5601104054
Formality 0706 User Guide	asic_zzz 2008-4-4	11 / 107	2008-5-28 11:47 by hitten
关于三端稳压器在线等谢谢	figle 2008-5-28	0 / 8	2008-5-28 11:17 by figle
关于VCS DVE调式环境的问题	reset_n 2008-5-25	2 / 27	2008-5-27 21:46 by jiancongwoo
帮帮忙，如何调用库中带使能的触发器？	anty4111981 2008-5-27	2 / 38	2008-5-27 21:11 by qingchuyu

4765 1 ...‹‹7 8910 11 12 13 14 15 16 ››... 96

有新回复

无新回复

热门主题

关闭主题