testbench入门

标题	作者	回复/查看	最后发表
和大家分享	cooking12 2008-4-3	4 / 52	2008-5-6 15:40 by xiaoai_sh
writing testbench charp8	mamade52 2008-3-11	7 / 46	2008-4-29 09:26 by braveknight
sdafsadf	tangkaizj 2008-4-24	1 / 4	2008-4-29 09:25 by braveknight
继续再发一个，希望对大家有用	yuliangelsigh 2008-3-27	8 / 78	2008-4-29 09:24 by braveknight
writing testbench charp2	mamade52 2008-3-11	5 / 49	2008-4-29 09:23 by braveknight
阿萨	tangkaizj 2008-4-24	1 / 11	2008-4-29 09:23 by braveknight
test bench 详细步骤 1 2	gmtang97129 2008-2-27	38 / 651	2008-4-24 13:59 by xiaozhu
也来发个testbench的帖子	yuliangelsigh 2008-3-27	6 / 84	2008-4-23 07:25 by huangwarren
我想再写testbench时输入输出数据该怎么做呢？	HolySaint 2008-4-12	2 / 63	2008-4-21 14:54 by tomersun
[500EDA元]求个cic的verilog的testbench附代码	HolySaint 2008-4-12	3 / 48	2008-4-12 23:44 by HolySaint
好东西！	mamade52 2008-3-10	8 / 71	2008-4-12 20:05 by yuchenny
writing testbench charp7	mamade52 2008-3-11	5 / 35	2008-4-8 10:12 by nong.hero
writing testbench charp6	mamade52 2008-3-11	5 / 30	2008-4-8 09:49 by nong.hero
为什么modelsim前仿真出的波形都是直线	dad 2008-3-7	3 / 73	2008-4-1 16:19 by asyou
writing testbench charp5	mamade52 2008-3-11	3 / 26	2008-4-1 14:35 by JJL1212
给点VHDL测试代码啊	zhuxuxiaojie 2008-3-12	1 / 41	2008-3-12 22:29 by zhuxuxiaojie
writing testbench charp2	mamade52 2008-3-11	0 / 18	2008-3-11 22:03 by mamade52
testbench好难呀，语法灵活	renconghui 2008-1-6	8 / 182	2008-3-5 23:14 by brooks
testbench writing	traeumerling 2008-1-15	1 / 65	2008-3-1 14:53 by dzpcn
verilog vhdl混合仿真	tony_dun 2008-1-11	3 / 69	2008-2-22 20:24 by zylyh1
发个testbench资料，不要钱	bluesteep 2007-12-25	19 / 423	2008-2-21 13:35 by fanlv
testbench 中文经典教程包括VHDL 和verilog 1 2	zgj341 2007-12-19	38 / 829	2008-2-13 10:41 by autokyo
有人能提供writing testbech的资料或者是书吗?	corvinqiao 2007-12-6	8 / 91	2008-1-29 21:10 by geffio
编写高效率的testbench.pdf	liang_arthur 2007-11-29	24 / 382	2008-1-25 22:33 by yyld
怎么新建testbench文件？	flyfpga 2007-12-8	10 / 120	2008-1-25 22:26 by yyld
请问各位高人RS编码器的仿真文件该怎么写？有仿真模型吗？	dldlnrml 2008-1-21	0 / 12	2008-1-21 21:47 by dldlnrml
有没有做验证的?	zj_ic 2008-1-11	1 / 25	2008-1-20 16:38 by lovystory
怎样生成Modelsim需要的.VEC激励文件？	xiaojuchina 2007-12-3	1 / 69	2008-1-16 20:20 by zlzhou
how to start a testbench in ISE9.1	traeumerling 2008-1-15	0 / 30	2008-1-15 04:18 by traeumerling
写好的testbench 文件到底怎么运行啊?	zgj341 2007-12-19	5 / 127	2008-1-10 17:16 by jack_FPGA
本人想学modulesim	renconghui 2007-12-24	2 / 33	2008-1-6 21:08 by renconghui
为什么有的帖子不能回复呢？	lingzhi66 2008-1-3	0 / 8	2008-1-3 13:02 by lingzhi66
本人想学testbench,请指教	renconghui 2007-12-24	4 / 70	2008-1-2 10:52 by brightisle
MCU 基础	sgl6688 2007-12-31	0 / 41	2007-12-31 16:37 by sgl6688
为什么加入timescale会报错？	xiaocat85 2007-12-6	8 / 68	2007-12-24 09:35 by 清风熊
求助：用什么能使c和verilog结合起来	avalia 2007-11-21	4 / 93	2007-12-19 17:44 by joyjie
郁闷死了，哪位高手给解决一下阿，急!!!!!! testbench错误	ninghuiming 2007-12-17	2 / 52	2007-12-18 16:56 by ninghuiming
询问：什么地方或者有什么资料可以找点一下比较常用的标准化的testbench	avalia 2007-11-19	5 / 102	2007-12-17 20:14 by ninghuiming
想问一下 tb里的输入是怎么设置的呢	songfei836 2007-12-17	1 / 30	2007-12-17 13:15 by songfei836
问题	1252905477 2007-12-16	0 / 10	2007-12-16 11:32 by 1252905477
状态机 modelsim后仿真出现问题	xyj1984214 2007-12-15	0 / 22	2007-12-15 20:53 by xyj1984214
textio文件	zhongyunde 2007-12-10	0 / 88	2007-12-10 23:04 by zhongyunde
hao hao hao	ciappcia 2007-12-8	0 / 20	2007-12-8 10:04 by ciappcia
太好了	陈小林 2007-11-16	2 / 29	2007-12-8 10:01 by ciappcia
哄MM用这招还真管用a	ddeedd 2007-10-13	4 / 125	2007-12-8 00:46 by rvisk
zzzz	zj_ic 2007-12-7	1 / 12	2007-12-8 00:46 by rvisk
推介Modeling with SystemVerilog in a Synopsys Synthesis Design Flow Using ...	vinz 2007-9-11	2 / 152	2007-10-28 21:10 by chinahuman
testbench仿真问题~！	xdxz 2007-10-15	0 / 107	2007-10-15 14:29 by xdxz
有用于仿真调用ip核的testbench（verilog编写的）资料吗	skywwang 2007-8-24	3 / 91	2007-10-13 02:17 by downgood
modelsim中使用$finish(2) 返回的时间不对，请教高手	fogcc 2007-9-27	1 / 32	2007-10-13 02:07 by downgood

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