模拟设计经验100条===============================================================================1/ Capacitors and resistors have parasitic inductance, about 0.4nH for surface mount and 4nH for a leaded component.2/ If you don"t want a high bandwidth transistor to oscillate place lossy co
看了一latch-up效应的资料Latch up 的定义􀂃 Latch up 最易产生在易受外部干扰的I/O电路处, 也偶尔发生在内部电路􀂃 Latch up 是指cmos晶片中, 在电源power VDD和地线GND(VSS)之间由于寄生的PNP和NPN双极性BJT相互影响而产生的一低阻抗通路, 它的存在会使VDD和GND之间产生大电流h