Mux : Using with Statement
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1 -------------------------------------------------------1 N7 `/ }% }% `% u0 F# F
2 -- Design Name : mux_using_with, H5 d$ n M- i4 p: P( U
3 -- File Name : mux_using_with.vhd; N, X2 {5 t; j. K) y8 X) b
4 -- Function : 2:1 Mux using with-select0 l8 O: u/ H: @0 d$ M
5 -- Coder : Deepak Kumar Tala (Verilog)0 p0 p) I' u- |
6 -- Translator : ******nder H Pham (VHDL)
! \- T5 a& r k0 m% s 7 -------------------------------------------------------+ h) {' p, f6 }" U' Q
8 library ieee;
) {1 v4 \& b6 t; R 9 use ieee.std_logic_1164.all;
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11 entity mux_using_with is$ U- ?- n1 A& E
12 port (
3 G! V1 b' b, n( U8 z1 _: O) W 13 din_0 :in std_logic;-- Mux first input
3 K9 Q1 _: X- ~1 [3 C" C* w 14 din_1 :in std_logic;-- Mux Second input
+ J" W. i! \. y: i* d 15 sel :in std_logic;-- Select input
/ K! S- U& C) S3 o& @! k# N 16 mux_out  ut std_logic -- Mux output
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+ y1 l8 H7 T1 Z7 U& d6 G+ v 19 end entity;
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9 \1 ~ S( ^: ~8 t8 K; f) b 21 architecture behavior of mux_using_with is
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23 begin
2 t& n+ b: ` p8 c6 x4 B 24 with (sel) select4 |$ q7 o, U% j1 E, g( z, M+ t
25 mux_out <= din_0 when '0',& R6 ~. i( W! C8 y! D7 ]
26 din_1 when others; |
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