元件配置
在引用
------------------------------------------------------------------------
-- N-bit adder
-- The width of the adder is determined by generic N
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity adderN is
generic(N : integer := 16);
port (a : in std_logic_vector(N downto 1);
b : in std_logic_vector(N downto 1);
cin : in std_logic;
sum : out std_logic_vector(N downto 1);
cout : out std_logic);
end adderN;
-- behavioral implementation of the N-bit adder
architecture behavioral of adderN is
begin
p1: process(a, b, cin)
variable vsum : std_logic_vector(N downto 1);
variable carry : std_logic;
begin
carry := cin;
for i in 1 to N loop
vsum(i) := (a(i) xor b(i)) xor carry;
carry := (a(i) and b(i)) or (carry and (a(i) or b(i)));
end loop;
sum <= vsum;
cout <= carry;
end process p1;
end behavioral;
时使用下面的配置方式
configuration test_adder_behavioral of testbench is
for adder8
for all: adderN
use entity work.adderN(behavioral);
end for;
end for;
end test_adder_behavioral;
提示 ** Error: D:/Program_Files/altera72/mywork/test/simulation/modelsim/testbench.vhd(137): (vcom-1002) Generic 'n' in component 'addern' does not exist in entity 'addern'.
# ** Error: D:/Program_Files/altera72/mywork/test/simulation/modelsim/testbench.vhd(139): VHDL Compiler exiting
怎么回事？现在把这个配置部分删除后，能通过编译
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