我遇到下面这个程序，理论分析为11分频，而仿真波形只有8分频！
请哪位大虾指出原因·谢谢！
library ieee;
use ieee.std_logic_1164.all;
entity speaker is
port(clk1:in std_logic;
          tone1:in integer range 0 to 16#7ff#;
          spksut std_logic;
          sdput std_logic);
end entity speaker;

architecture behav of speaker is
signal preclk,fullspks:std_logic;
begin

divideclk:process(clk1)
variable count4:integer range 0 to 15;
begin
preclk<='0';               --将clk 11分频 preclk 6分频
if count4>11 then  preclk<='1';
count4:=0;
elsif clk1'event and clk1='1' then count4:=count4+1;
end if;
sdp<=preclk;
end process;

genspks:process(preclk,tone1)
variable count11:integer range 0 to 16#7ff#;--11位可预置计数器
begin
if preclk'event and preclk='1' then
if count11=16#7ff# then
count11:=tone1;--置数
fullspks<='1';
else count11:=count11+1;
fullspks<='0';
end if;
end if;
end process;

delayspks:process(fullspks)
variable count2:std_logic;
begin
if fullspks'event and fullspks='1'
then count2:=not count2;
if count2='1' then spks<='1';
else spks<='0';
end if;
end if;
end process;
end architecture behav;
:funk::funk::funk::funk::funk:

是音乐播放设计吧！tone是音调控制量吧！

论坛里有关于基数分频的帖子 自己可以去看看

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fdiv3 is
port( clk  : in   std_logic;
             q : out  std_logic);
end fdiv3;
architecture  go  of fdiv3 is
signal cp1,cp : std_logic;
signal cnt,cnt1  : integer range 0 to 5;
begin
process(clk)
begin
if rising_edge(clk)  then
cnt<=cnt+1;
if cnt=1 then
cp<=not cp;
end if;
if cnt<=6 then
cp<=not cp;
end if;
if cnt=11 then
cnt<=1;
end if;
end if;
if clk 'event and clk='0'  then
cnt1<=cnt1+1;
if cnt1=1 then
cp1<=not cp1;
end if;
if cnt1<=6 then
cp1<=not cp1;
end if;
if cnt1=11 then
cnt<=1;
end if;
end if;
q<=(cp or cp1);
end process;
end go;
这个程序你试试，我还没调试过

看不懂看不懂