| a systemc primer | 1# |
| advanced verification methodology cookbook | 2# |
| an asic primer | 3# |
| analysis and design of analog integrated circuits, fourth edition | 45# |
| application-specific integrated circuits | 4# |
| asic design with synopsys | 41# |
| asynchronous circuit design | 43# |
| asynchronous fifo architectures | 5# |
| complete digital design | 6# |
| concepts, algorithms, and tools for model checking | 7# |
| design-for-test for digital ic's and embedded core systems | 8# |
| digital uart design in hdl | 9# |
| high speed design techniques | 10# |
| introduction to algorithms, second edition | 42# |
| pll performance, simulation, and design, third edition | 11# |
| principles of verifiable rtl design, second edition | 12# |
| reuse methodology manual for system-on-achip designs, third edition | 13# |
| synthesizable verilog syntax and semantics | 14# |
| system-on-a-chip verification methodology and techniques | 15# |
| systemverilog for verification | 16# |
| the crc handbook of modern telcommunications | 21# |
| verilog coding for logic synthesis | 17# |
| verilog hdl synthesis | 20# |
| Verilog hdl-a guide to digital design and synthesis, second edition | 1# |
| vhdl programming example, fourth edition | 18# |
| writing testbenches - functional verification of hdl models, second edition | 37# |
| writing testbenches using system verilog | 19# |
| writing testbenches, second edition | 38# |
