lfsr的fifo怎么改成verilog的
再做fifo时，看到有关的程序是用lfsr实现的，但是好像lfsr的位数是变化的，源程序是VHDL，而对那不是了解，有谁帮忙改一下，verilog的，谢谢
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_lfsr is
generic(
TAPS : positive range 16 downto 3 :=8;
OFFSET : natural := 0
);
port(
clk : in std_logic; -- clock input
ena : in std_logic; -- count enable
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
Q : out unsigned(TAPS downto 1); -- count value
Qprev : out unsigned(TAPS downto 1) -- previous count value
);
end entity atahost_lfsr;
architecture dataflow of atahost_lfsr is
function lsb(tap : positive range 16 downto 3; Q : unsigned(TAPS downto 1) ) return std_logic is
begin
case tap is
when 3 =>
return Q(3) xnor Q(2);
when 4 =>
return Q(4) xnor Q(3);
when 5 =>
return Q(5) xnor Q(3);
when 6 =>
return Q(6) xnor Q(5);
when 7 =>
return Q(7) xnor Q(6);
when 8 =>
return (Q(8) xnor Q(6)) xnor (Q(5) xnor Q(4));
when 9 =>
return Q(9) xnor Q(5);
when 10 =>
return Q(10) xnor Q(7);
when 11 =>
return Q(11) xnor Q(9);
when 12 =>
return (Q(12) xnor Q(6)) xnor (Q(4) xnor Q(1));
when 13 =>
return (Q(13) xnor Q(4)) xnor (Q(3) xnor Q(1));
when 14 =>
return (Q(14) xnor Q(5)) xnor (Q(3) xnor Q(1));
when 15 =>
return Q(15) xnor Q(14);
when 16 =>
return (Q(16) xnor Q(15)) xnor (Q(13) xnor Q(4));
end case;
end function lsb;
signal msb : std_logic;
signal iQ : unsigned(TAPS downto 1);
begin
--
-- generate register
--
gen_regs: process(clk, nReset)
variable tmpQ : unsigned(TAPS downto 1);
variable tmpmsb : std_logic;
begin
tmpQ := (others => '0');
tmpmsb := '1';
for n in 1 to offset loop
tmpQ := (tmpQ(TAPS -1 downto 1) & lsb(TAPS, tmpQ) );
tmpmsb := tmpQ(TAPS);
end loop;
if (nReset = '0') then
iQ <= tmpQ;
msb <= tmpmsb;
elsif (clk'event and clk = '1') then
if (rst = '1') then
iQ <= tmpQ;
msb <= tmpmsb;
elsif (ena = '1') then
iQ <= (iQ(TAPS -1 downto 1) & lsb(TAPS, iq) );
msb <= iQ(TAPS);
end if;
end if;
end process gen_regs;
-- assign outputs
Q <= iQ;
Qprev <= (msb & iQ(TAPS downto 2));
end architecture dataflow;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_fifo is
generic(
DEPTH : natural := 31; -- fifo depth, this must be a number according to the following range
-- 3, 7, 15, 31, 63 ... 65535
SIZE : natural := 32 -- data width
);
port(
clk : in std_logic; -- master clock in
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
rreq : in std_logic; -- read request
wreq : in std_logic; -- write request
empty : out std_logic; -- fifo empty
full : out std_logic; -- fifo full
D : in std_logic_vector(SIZE -1 downto 0); -- data input
Q : out std_logic_vector(SIZE -1 downto 0) -- data output
);
end entity atahost_fifo;
architecture structural of atahost_fifo is
--
-- function declarations
--
function bitsize(n : in natural) return natural is
variable tmp : unsigned(32 downto 1);
variable cnt : integer;
begin
tmp := conv_unsigned(n, 32);
cnt := 32;
while ( (tmp(cnt) = '0') and (cnt > 0) ) loop
cnt := cnt -1;
end loop;
return natural(cnt);
end function bitsize;
--
-- component declarations
--
component atahost_lfsr is
generic(
TAPS : positive range 16 downto 3 :=8;
OFFSET : natural := 0
);
port(
clk : in std_logic; -- clock input
ena : in std_logic; -- count enable
nReset : in std_logic; -- asynchronous active low reset
rst : in std_logic; -- synchronous active high reset
Q : out unsigned(TAPS downto 1); -- count value
Qprev : out unsigned(TAPS downto 1) -- previous count value
);
end component atahost_lfsr;
constant ADEPTH : natural := bitsize(DEPTH);
-- memory block
type memory is array (DEPTH -1 downto 0) of std_logic_vector(SIZE -1 downto 0);
-- shared variable mem : memory; -- VHDL'93 PREFERED
signal mem : memory; -- VHDL'87
-- address pointers
signal wr_ptr, rd_ptr, dwr_ptr, drd_ptr : unsigned(ADEPTH -1 downto 0);
begin
-- generate write address; hookup write_pointer counter
wr_ptr_lfsr: atahost_lfsr
generic map(
TAPS => ADEPTH,
OFFSET => 0
)
port map(
clk => clk,
ena => wreq,
nReset => nReset,
rst => rst,
Q => wr_ptr,
Qprev => dwr_ptr
);
-- generate read address; hookup read_pointer counter
rd_ptr_lfsr: atahost_lfsr
generic map(
TAPS => ADEPTH,
OFFSET => 0
)
port map(
clk => clk,
ena => rreq,
nReset => nReset,
rst => rst,
Q => rd_ptr,
Qprev => drd_ptr
);
-- generate full/empty signal
full <= '1' when (wr_ptr = drd_ptr) else '0';
empty <= '1' when (rd_ptr = wr_ptr) else '0';
-- generate memory structure
gen_mem: process(clk)
begin
if (clk'event and clk = '1') then
if (wreq = '1') then
mem(conv_integer(wr_ptr)) <= D;
end if;
end if;
end process gen_mem;
Q <= mem(conv_integer(rd_ptr));
end architecture structural;
[ 本帖最后由 pengyouxiaohui 于 2008-5-5 12:09 编辑 ]
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