使用Synplify对下面一段代码进行综合时，出现了这样的错误：All event expressions in an always statement must be identical
到底是什么意思呢？应该怎样修改？
请教高手指教，先谢谢啦～

代码：
`timescale 1ns/1ns
`define timeslice 100
module shift_in(clk,rstn,scl,sda,data_out,out_flag,sda_buf);
    input clk,rstn,scl,sda;
    output out_flag,sda_buf;
    output [7:0] data_out;
    reg  out_flag,sda_buf;
    reg [7:0] data_out;
   
    always @(posedge clk)
    if(!rstn)
    data_out=8'd0;
    else
    shift_in(data_out);
   
    task shift_in;
    output [7:0] shift;
    begin
     @ (posedge  scl) shift[7] = sda;  
     @ (posedge  scl) shift[6] = sda;
     @ (posedge  scl) shift[5] = sda;
     @ (posedge  scl) shift[4] = sda;
     @ (posedge  scl) shift[3] = sda;
     @ (posedge  scl) shift[2] = sda;
     @ (posedge  scl) shift[1] = sda;
     @ (posedge  scl) shift[0] = sda;
     @ (negedge scl)      
       begin  
         #`timeslice ;
        out_flag = 1;   
          sda_buf  = 0;  
       end
     @(negedge scl)
        #`timeslice out_flag  = 0;  
    end
endtask
  
endmodule

所报的错：
@E:"D:/Synplicity/EEPROM\shift_in.v":10:13:10:23|All event expressions in an always statement must be identical
@E:"D:/Synplicity/EEPROM\shift_in.v":19:8:19:19|All event expressions in an always statement must be identical
@E:"D:/Synplicity/EEPROM\shift_in.v":20:8:20:19|All event expressions in an always statement must be identical
@E:"D:/Synplicity/EEPROM\shift_in.v":21:8:21:19|All event expressions in an always statement must be identical
@E:"D:/Synplicity/EEPROM\shift_in.v":22:8:22:19|All event expressions in an always statement must be identical
@E:"D:/Synplicity/EEPROM\shift_in.v":23:8:23:19|All event expressions in an always statement must be identical
@E:"D:/Synplicity/EEPROM\shift_in.v":24:8:24:19|All event expressions in an always statement must be identical
@E:"D:/Synplicity/EEPROM\shift_in.v":25:8:25:19|All event expressions in an always statement must be identical
@E:"D:/Synplicity/EEPROM\shift_in.v":26:8:26:19|All event expressions in an always statement must be identical
@E:"D:/Synplicity/EEPROM\shift_in.v":27:8:27:18|All event expressions in an always statement must be identical
@E:"D:/Synplicity/EEPROM\shift_in.v":33:7:33:17|All event expressions in an always statement must be identical

这是个测试代码
Synplify是针对可综合代码的

不可综合的是报warning吧..忘记了

Putting test pattern aside. I'm talking about your rtl. Your code is very much wrong...

task shift_in;    // task is defining an operation, you don't need to specify the output
    output [7:0] shift;  // you need to define input but not output here
...
...
...
if your task has sequential logic, it's unsynthesizable.

always @(posedge clk)
    if(!rstn)
    data_out=8'd0;
    else
    shift_in(data_out); // you may write in this way data_out = shift_in( input1, input2,....), make sure your task is pure combinational logic

Here you're describing a dff, make sure the output name is the same.  If you want to pass a value to the dff propagating through some complex combination logic, better to use an FUNCTION but not TASK. If you want to pass a value to the dff which is from sequential logic, better to define another module, but not use FUNCTION or TASK.
Actually, TASK is very rare to be used in RTL, usually in Test bench.

task那段是夏宇闻书中一个实例中的一段，在整段代码进行综合时就会报以上的错，原来的代码太长了，所以我只把task这段拿了出来，修改了一下放上来了
很想知道为什么会出现“All event expressions in an always statement must be identical”的错误，到底是什么意思呢？
请各位高手继续指点啊

Don't you know the meaning of  "identical"??

知道啊，可是不明白为什么会出错

楼主看书认真些
都说过了,这是行为级描述,仿真可以,不能综合的
我帮你翻了下书
夏宇闻关于I2C那章
你好好阅读一下这代码的注释,已经提醒你不能综合了

知道不可以综合，想把它修改成可以综合的

我只是很想知道这个错误的原因
仅仅是因为它是行为级描述吗？

原因很简单，综合器无法把你的代码映射成电路。

在xilinx中可以运行测试模块。。。

一下各位大侠为什么vhdl里

@ (posedge  scl) shift[1] = sda这种语句只会出现在仿真中！你要修改一下！

楼主还是刚入门吧

楼主的这种学习习惯可是不好啊！