Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

--use work.SIGNED_ARITH.all;

use work.coeffs.all;

entity fir is
port( clk,reset: in std_logic;

sample: in signed ( 7 downto 0);

result: out signed ( 16 downto 0));
end fir;

architecture beh of fir is
begin

fir_main :process

type shift_arr is array (16 downto 0) of signed (7 downto 0);

variable tmp,old:signed( 7 downto 0);

variable pro:signed (16 downto 0);

variable acc:signed (16 downto 0);

variable shift:shift_arr;
     

begin

reset_loop:loop

for i in 0 to 15 loop --zero out the shift register

shift(i):=(others=>'0');

end loop;

result<=(others=>'0');

wait until clk'event and clk='1';

if reset='1' then exit reset_loop;

end if;


main:loop

tmp:=sample;

pro:=tmp*coefs(0);

acc:=pro;

for i in 15 downto 0 loop

old:=shift(i);

pro:=old*coefs(i+1);

acc:=acc+pro;

shift(i+1):=shift(i);

end loop;

shift(0):=tmp;

result<=acc;

wait until clk'event and clk='1';

if reset='1' then exit reset_loop;

end if;

end loop main;

end loop reset_loop;

end process;

end beh;
编译时出现下列错误：
Error (10398): VHDL Process Statement error at fir.vhd(46): Process Statement must contain only one Wait Statement
进行定位后发现错位在
这一段中的wait until语句
wait until clk'event and clk='1';

if reset='1' then exit reset_loop;

end if;
程序在modelsim中没有错误，但是在转换到Quartus中出现这样的错误，如何修改？？谢谢！

如果想改成在process中添加激励信号clk和reset信号，如何修改程序代码？

process
   begin
    wait for 10 ns
   clk = '0';
   wait for 10 ns
   clk = '1';
  end process

????????

不可综合语句吧..modelsim不在乎你的语句是否可以综合.......

modelsim只能做一些仿真，不能产生sof。pof文件的？是不是这样的？

应该是wait until clk='1'吧，或是if clk'event and clk='1' then...吧，有的语句是不能综合的，modelsim只是一个仿真软件

if clk'event and clk='1' then...

这种格式该怎么修改呢？

这个语句的意思就是等到clk的上升沿来到时要作什么，就把你下面要执行的代码写上