TRANSLATE_OFF and TRANSLATE_ON 的作用
TRANSLATE_OFF and TRANSLATE_ON Applicable Elements
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7 I1 Q9 _ ]' m: t5 }TRANSLATE_OFF and TRANSLATE_ON can be applied locally only.# c8 I# K8 {9 Z- K `7 _. i
TRANSLATE_OFF and TRANSLATE_ON Description
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( l- Y& q# f8 M( |, {TRANSLATE_OFF and TRANSLATE_ON are synthesis constraints. Use TRANSLATE_OFF and TRANSLATE_ON to instruct XST to ignore portions of your VHDL or Verilog code that are not relevant for synthesis—for example, simulation code. The TRANSLATE_OFF directive marks the beginning of the section to be ignored and the translate_on directive instructs XST to resume synthesis from that point." o4 b y! o b) j+ z' l
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Note: The constraints TRANSLATE_OFF and TRANSLATE_ON are also Synplicity and Synopsys constraints that are supported by XST in Verilog. Automatic conversion is also available in VHDL and Verilog.& j7 T9 X- g* j# F
/ ~" ?) y% u8 K0 n- _Note: translate_on/translate_off could be used with the following words:
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# x, Z& N4 C5 t- k; q6 A * synthesis/ k+ C4 r" R# b& D7 {
* synopsys4 C0 M+ f6 u9 M
* pragma
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TRANSLATE_OFF and TRANSLATE_ON Propagation Rules
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6 l6 w6 X T- }2 x% G% l1 VInstructs synthesis tool to enable or disable portions of code.
# ^0 b2 S3 v3 z$ K2 @TRANSLATE_OFF and TRANSLATE_ON Syntax Examples
: T, w& ^# O( T- i8 D9 gSchematic
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$ Z+ X; I4 B7 ]Not applicable.
9 ~- |3 r* _/ f( g; |; ~VHDL* G L2 ~- |' e4 ~
! j7 ~2 o. \/ l( d6 c9 `+ UIn your VHDL code, the directives should be written as follows:' ~' X6 S0 z( O) B! y. \# A7 Z- I( y
-- synthesis translate_off4 T: M' a6 U' v1 a* O5 i1 A
...code not synthesized...! S( w- {; R* b7 W6 m3 C
-- synthesis translate_on- J) Z" K& f$ v& |9 j; e n/ B
9 v" d0 D. b# HFor a detailed discussion of the basic VHDL syntax, see “VHDL”.: q$ s7 a4 h3 p7 w' t
Verilog
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5 I: f L% u; m/ \The directives are available as VHDL or Verilog meta comments. The Verilog syntax differs from the standard meta comment syntax presented earlier in this chapter, as shown below.8 [# i% P' Y% i \
// synthesis translate_off
J5 Z6 x; V: n9 }# y...code not synthesized...
2 r$ {9 @2 B' Z/ U8 s) |; L9 D& ?// synthesis translate_on: X7 ~0 ]8 n4 S3 \3 c
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For a detailed discussion of the basic Verilog syntax, see“Verilog”.
