我的系统时钟在顶层用bufg原语驱动，在synplify综合后看也是综合成了bufg，但是在ise的map是有警告说bufgmux symbol have a mix of clock and no-clock loads，用chipscope看bufg出来的时钟有时就没有了，不知是什么原因，在virtex2中是不是bufg和bufgmux实际是同一个物理单元，如何能让从bufg出来的时钟始终是好的

[这个贴子最后由fgb在 2005/07/20 12:59pm 第 1 次编辑]

怎么，都不知道

不是同一个物理单元
BUFGMUX is a multiplexed global clock buffer that can select between two input　clocks I0 and I1. When the select input (S) is Low, the signal on I0 is selected for　output (O). When the select input (S) is High, the signal on I1 is selected for output.　BUFGMUX and BUFGMUX_1 are　distinguished by which state the output assumes　when it switches between clocks in response to a change in its select input.
BUGFMUX assumes output state 0 and BUFGMUX_1 assumes output state 1.
Using a BUFGMUX element in your design may cause inaccurate simulation if all the　following conditions occur: both clock inputs (I0 and I1) are used, GSR is activated　during simulation (after simulation time ‘0’), and the secondary clock input (I1) is　selected before or while GSR is active. In this case, the primary clock input (I0) is　incorrectly selected. This occurs because there is a cross-coupled register pair that
ensures the BUFGMUX output does not inadvertently generate a clock edge. When　GSR is asserted, these registers initialize to the default state of I0. To select the　secondary clock, you must send a clock pulse to both the primary and secondary　clock inputs while GSR is inactive.
Note: BUFGMUX guarantees that when S is toggled, the state of the output will remain in the　inactive state until the next active clock edge (either I0 or I1) occurs.