就是实现了5bit补码的加减法啊
; ^" d0 j5 S6 D6 L! r" L7 Kentity bm_calculate_rc is
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Port (
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clk : in std_logic;
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branch_out: in std_logic_vector(1 downto 0);
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code_in : in std_logic_vector(5 downto 0);
3 l2 C' {* [- S8 N4 d branch_metric
ut std_logic_vector(4 downto 0)
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);
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end bm_calculate_rc;
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architecture Behavioral of bm_calculate_rc is
$ ^7 b0 `, f7 }" Q3 X- jcomponent adder55 is
- D* E" I8 y, {5 D; z! S5 { Port (a:IN std_logic_vector(4 downto 0);
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b:IN std_logic_vector(4 downto 0);
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add_result:OUT std_logic_vector(4 downto 0));
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end component;
6 i, N* }5 I! w2 v7 r, v& b7 ]--signal branch_out_reg : std_logic_vector( 1 downto 0):="00";
& `7 D0 o8 o% [0 m( W- A! ?signal branch_metric_reg : std_logic_vector( 4 downto 0):="00000";
4 }" a' P/ V3 o, A* c3 T3 N4 fsignal branch_metric_reg00 : std_logic_vector( 4 downto 0):="00000";
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signal branch_metric_reg01 : std_logic_vector( 4 downto 0):="00000";
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signal branch_metric_reg10 : std_logic_vector( 4 downto 0):="00000";
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signal branch_metric_reg11 : std_logic_vector( 4 downto 0):="00000";
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signal in1: std_logic_vector( 4 downto 0):="00000";
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signal in2: std_logic_vector( 4 downto 0):="00000";
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signal in2_buma: std_logic_vector( 4 downto 0):="00000";
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signal branch_metric_reg_reg00 : std_logic_vector( 4 downto 0):="00000";
. ]2 Y7 I- X2 t6 o, ? ]. psignal branch_metric_reg_reg01 : std_logic_vector( 4 downto 0):="00000";
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begin
( W$ U. W B$ l0 k process(clk)
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begin
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if clk'event and clk='1' then
0 T- H) v5 t* x7 @if code_in(5 downto 5)="0" then
0 H5 b6 b7 W" ]( u! g in1<="00"&code_in(5 downto 3);
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else
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in1<="11"&code_in(5 downto 3);
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end if;
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end if;
4 o* h- x7 u/ a- j end process;
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process(clk)
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begin
2 X9 Y5 V$ s. W" [+ L if clk'event and clk='1' then
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if code_in(2 downto 2)="0" then
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in2<="00"&code_in(2 downto 0);
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in2<="11"&code_in(2 downto 0);
: U/ O, p7 t, N; a5 y% ?* x) t, ] end if;
" |9 P |. [* `; d' \% {9 N end if;
# v. R# H7 A3 g1 x end process;
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bm_calculate00: adder55
' \+ E7 L4 Z; e port map (a=>in1,
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b=>in2,
$ T" D; E8 h6 l. F$ ~- ?add_result=>branch_metric_reg_reg00);
; ]+ @3 b( q$ m. }+ X in2_buma<=not (in2) +'1';
t8 r" w9 k. g$ Cbm_calculate01: adder55
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port map (a=>in1,
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b=>in2_buma,
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add_result=>branch_metric_reg_reg01);
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/ O' [: O. j9 Q/ L; L* W branch_metric_reg00 <= branch_metric_reg_reg00;
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branch_metric_reg01 <= branch_metric_reg_reg01;
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branch_metric_reg10 <= not(branch_metric_reg_reg01)+'1';
# |* j3 C6 Y7 J/ S9 a5 g' u y branch_metric_reg11 <= not(branch_metric_reg_reg00)+'1';
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process( clk)
* y. W4 w/ W0 ~2 T2 ~ begin
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if clk'event and clk='1' then
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case branch_out is
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when "00" => branch_metric_reg<=branch_metric_reg00;
5 L4 c$ r- x6 _- o3 v. p when "01" => branch_metric_reg<=branch_metric_reg01;
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when "10" => branch_metric_reg<=branch_metric_reg10;
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when "11" => branch_metric_reg<=branch_metric_reg11;
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when others=> branch_metric_reg<="00000";
( @: N. E1 J0 u# i9 B4 s0 S end case;
# V) T) B9 L( i8 e end if;
7 A D% b* ?) F; V end process;
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branch_metric<=branch_metric_reg;
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end Behavioral;
