Power-up仿真时把BUFGMUX的输入端设为“S=1”,输出不定态，直到i1出现下降沿，之后BUFGMUX才被设置为i1，不知道这样的仿真结果有没有问题？

根据virtexII的文档，BUFGMUX确实要等到两个输入时钟都相继为低电平以后才进行时钟切换，所以在i1出现下降沿之后BUFGMUX才被设为i1是合理的，切换前输出不定态就好像说不过去了。
另外，你的BUFGMUX是用什么综合工具综合出来的，我试过用synplify，但似乎synplify支持不了？

xilinx 的回答，碰巧看到，转贴过来：
Solution 1:

The simulation behavior is correct -- BUFGMUX always powers up with "I0" selected. Consequently, if "S=1" at "time=0", I0 is immediately de-selected as output and I1 is selected at its next falling edge.
The result is illustrated in the above simulation.
The BUFGMUX output O will be logic level "0" (GND) when S is changing from I0 to I1, and vice-versa.
For more information on BUFGMUX behavior, please see the Virtex-II/Pro User Guides: Chapter 2, "Design Considerations" -> Using a Global Clock Network:
For Virtex-II Pro:
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/FPGA+Device+Families/Virtex-II+Pro&iLanguageID=1
For Virtex-II:
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/FPGA+Device+Families/Virtex-II&iLanguageID=1