LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4_1 IS
PORT(a,b,c,d:IN STD_LOGIC;
s:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Y:OUT STD_LOGIC
);
END mux4_1;
ARCHITECTURE one of mux4_1 IS
BEGIN
PROCESS(s)
BEGIN
CASE s IS
WHEN"000"=>Y<=a;
WHEN"001"=>Y<=b;
WHEN"010"=>Y<=c;
WHEN"011"=>Y<=d;
WHEN OTHERS=>Y<='0';
END CASE;
END PROCESS;
END one;
