latch解决方法[摘自XILINX问答]

Keywords: HDL Advisor

Urgency: Standard

General Description:
When a latch inference is discovered during HDL synthesis, XST reports the following HDL Advisor message:

"WARNING:Xst:737 - Found n-bit latch for signal <name>."

The listing for "n" is the width of the latch.

If latch inference is intended, you can safely ignore this message. However, some inefficient coding styles can lead to accidental latch inference. You should analyze your code to see if this result is intended. The examples below illustrate how you can avoid latch inference.

解决方案 1:

Include all possible cases in the case statement.

Verilog

always @ (SEL or DIN1 or DIN2)
begin
case (SEL)
2'b00 : DOUT <= DIN1 + DIN2;
2'b01 : DOUT <= DIN1 - DIN2;
2'b10 : DOUT <= DIN1;
endcase
end

VHDL

process (SEL, DIN1, DIN2)
begin
case SEL is
when "00" => DOUT <= DIN1 + DIN2;
when "01" => DOUT <= DIN1 - DIN2;
when "10" => DOUT <= DIN1;
end case;
end process;

These two examples create latches because there is no provision for the case when SEL = "11." To eliminate the latches, add another entry to deal with this possibility.

Verilog

2'b11 : DOUT <= DIN2;

VHDL

when "11" => DOUT <= DIN2;

Using the "DEFAULT" (Verilog) or "WHEN OTHERS" (VHDL) clause always works, but this can create extraneous logic. This is always the safest methodology, but might produce a larger and slower design since any unknown state has logic that is needed to bring it to a known state.

解决方案 2:

Assign to all the same outputs in each case.

Verilog

always @ (SEL or DIN1 or DIN2)
begin
case (SEL)
2'b00 : DOUT <= DIN1 + DIN2;
2'b01 : DOUT <= DIN1 - DIN2;
2'b10 : DOUT <= DIN1;
2'b11 :
begin
DOUT <= DIN2;
TEMP <= DIN1;
end
endcase
end

VHDL

process (SEL, DIN1, DIN2)
begin
case SEL is
when "00" => DOUT <= DIN1 + DIN2;
when "01" => DOUT <= DIN1 - DIN2;
when "10" => DOUT <= DIN1;
when "11" =>
DOUT <= DIN2;
TEMP <= DIN1;
end case;
end process;

These examples infer latches because the "11" case assigns two outputs, while the others assign only one. Looking at this case from TEMP's point of view, only one of four possible cases are specified, so it is incomplete. You can avoid this situation by assigning values to the exact same list of outputs for each case.

解决方案 3:

Make sure any "if / else if" statements have a concluding "else" clause:

VHDL:

<code>
process (ge, din) is begin
if (ge = '1') then
dout_a <= din;
else
dout_a <= '0'; -- This is a concluding "else" statement.
end if;
end process;
</code>

Verilog:

<code>
always @(ge or din)
if (ge) dout_a <= din;
else dout_a <= 1'b0; // This is a concluding "else" statement.
</code>