我这程序哪里出现问题了

我在实现一个算法时，使用多个模块进行设计，各个模块进行时序仿真时都能得到自己想要的结果，而当我把几个模块综合到一起的时候，仿真时得不到正确的结果，这是什么原因？
程序如下：

library ieee;
use ieee.std_logic_1164.all;
package my_data is
  type inte_arry is array (0 to 15,0 to 1) of integer range 0 to 15;
  type inte_arry1 is array ( 0 to 7,0 to 1) of integer range 0 to 15;
  type inte_arry2 is array ( 0 to 3, 0 to 1) of integer range 0 to 15;
procedure c1 (signal in1:in inte_arry;
              variable out1,out2:inout inte_arry1;
              variable n1:in integer range 0 to 7
              );
end my_data;


package body my_data is
procedure c1(
                signal in1:in inte_arry;
                variable out1,out2:inout inte_arry1;
                variable n1:in integer range 0 to 7
  ) is


variable m,k2,k1:integer range 0 to 15;

variable p1,p2:integer range 0 to 1;

variable h1,h2:integer range 0 to 7;

begin
h1:=n1;h2:=n1;k2:=0;
   m:=out2(h2,1);
   if(m mod 2=0) then           ----------输入异
       m:=m+1;
      else m:=m-1;
    end if;

for k in 0 to n1 loop
  if out1(k,1)=m then
  k2:=1;
     exit;
else k2:=0;
   end if;
end loop;

if k2 =0 then

for k in 0 to 15 loop
  if in1(k,1)=m then
  h1:=h1+1;
   out1(h1,0):=in1(k,0);out1(h1,1):=in1(k,1);
     exit;
   end if;
  end loop;

-----xia------
   m:=out1(h1,0);
   if(m mod 2=0) then           ----------输入异
       m:=m+1;
      else m:=m-1;
    end if;

   h2:=h2+1;
   out2(h2,0):=in1(m,0);out2(h2,1):=in1(m,1);

else----if k2 =0 then

--------------------------进行选择点
for k in 2 to 15 loop
p1:=0;p2:=0;k1:=k;
   for j in 0 to n1 loop         ------判断是否在out1，out2中
    if (out1(j,0)=k ) then
           p1:=1;                           
           EXIT;
     else p1:=0;
      end if;
     if (out2(j,0)=k ) then
           p2:=1;                              
        exit;
     else p2:=0;
     end if;
    end loop;   --for j in 0 to 7 loop                 ------判断是否在out1，out2中
  if (p1+p2)=0 then
   exit;
  end if;
end loop;     ----for k in 2 to 15 loop

h1:=h1+1;
out1(h1,0):=in1(k1,0);out1(h1,1):=in1(k1,1);

   m:=out1(h1,0);
   if(m mod 2=0) then           ----------输入异
       m:=m+1;
      else m:=m-1;
    end if;

  h2:=h2+1;
  out2(h2,0):=in1(m,0);out2(h2,1):=in1(m,1);

------------------------- 进行选择点

end if;  --if k2 =0 then

--n1:=n1+1;

end c1;
end my_data;







----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.my_data.all;

entity zonghe is

port( clk:in std_logic;
       in_data:in inte_arry;

      cent1, cent2, cent3, cent4ut inte_arry2
        );
end entity;


architecture om of zonghe is

component cycle port(s1,s2,s3,s4:in inte_arry2;
      c1,c2,c3,c4: out inte_arry2 );
end component cycle;


component fen2 port(clk:in std_logic;
       in_data:in inte_arry1;
       out_1,out_2ut inte_arry2);
end component fen2;

component paixu port(clk:in std_logic;
in_data:in inte_arry1;
     out_dataut inte_arry1);

end component paixu;

signal b1,b2:inte_arry1;
signal b10,b20:inte_arry1;

signal c01,c02,c11,c12:inte_arry2;
signal n1:integer range 0 to 7;
begin


process(in_data,clk)
variable n1:integer range 0 to 7;
variable b11,b22: inte_arry1;
begin
n1:=0;
if (clk='1' and clk'event) then
b11(0,0):=in_data(0,0);b11(0,1):=in_data(0,1);
b22(0,0):=in_data(1,0);b22(0,1):=in_data(1,1);
for i in 1 to 7 loop
n1:=i-1;
c1(in_data,b11,b22,n1);


end loop;


for i in 0 to 7 loop

b1(i,0)<=b11(i,0);b1(i,1)<=b11(i,1);
b2(i,0)<=b22(i,0);b2(i,1)<=b22(i,1);

end loop;
end if;
end process;

p1: paixu port map(clk,b1,b10);

p2: paixu port map(clk,b2,b20);

f1:  fen2 port map(clk,b10,c01,c02);
f2:  fen2 port map(clk,b20,c11,c12);

c1:  cycle port map (c01,c02,c11,c12,cent1, cent2, cent3, cent4);


end om;