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Digital VLSI Design with Verilog(经典数字设计书)

字体: 小 中 大 | 打印 发表于: 2008-10-14 11:45    作者: dragonman    来源: EDA中国门户网站

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project.

In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs.

Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the accompanying CD-ROM. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.

A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.

Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parity and ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered.[attach]46805[/attach

[ 本帖最后由 dragonman 于 2008-10-17 14:22 编辑 ]

Digital VLSI Design with Verilog.part1.rar
(2008-10-14 11:45:44, Size: 1.95 MB, Downloads: 90)


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  • dragonman (2008-10-14 11:47:36)

    第二部分的

    Digital VLSI Design with Verilog.part2.rar
    (2008-10-14 11:47:36, Size: 1.95 MB, Downloads: 50)

  • dragonman (2008-10-14 11:48:28)

    第三部分的

    Digital VLSI Design with Verilog.part3.rar
    (2008-10-14 11:48:28, Size: 1.95 MB, Downloads: 49)

  • dragonman (2008-10-14 11:49:03)

    第四部分的

    Digital VLSI Design with Verilog.part4.rar
    (2008-10-14 11:49:03, Size: 1.95 MB, Downloads: 39)

  • dragonman (2008-10-14 11:49:57)

    第五部分，整本书完毕！

    Digital VLSI Design with Verilog.part5.rar
    (2008-10-14 11:49:57, Size: 1.91 MB, Downloads: 37)

  • zhangzhenyu (2008-10-14 15:50:50)

    发贴挣点钱吧

  • zhangzhenyu (2008-10-14 15:52:09)

    谢谢dragon man!

  • 柏颖 (2008-10-14 15:55:12)

    呵呵
    先下了
    谢啦~~

  • dragonman (2008-10-14 16:53:10)

    兄弟姐妹们，本书需要5部分全部下载才可以解压缩的，只有第一部分卖了点钱，其余4部分不收钱。兄弟我也是穷疯了，所以收了一点点。

  • dragonman (2008-10-14 16:54:10)

    下载了，请顶帖子！

    开卷有益，更要顶帖子！

  • keenboyee (2008-10-14 17:01:04)

    没钱了灌水啊，真郁闷啊

  • keenboyee (2008-10-14 17:02:04)

    不是说部要钱吗怎么出现
    EDA专业论坛 提示信息

    对不起，您的操作将会导致您的 EDA元 低于系统规定的下限值 0 元，请返回修正后重新提交。

  • keenboyee (2008-10-14 17:02:34)

    兄弟姐妹们，本书需要5部分全部下载才可以解压缩的，只有第一部分卖了点钱，其余4部分不收钱。兄弟我也是穷疯了，所以收了一点点。

  • keenboyee (2008-10-14 17:03:04)

    下载了，请顶帖子！

    开卷有益，更要顶帖子！

  • keenboyee (2008-10-14 17:04:11)

    好书
    谢谢dragon man!


    顶顶顶顶顶顶顶顶顶顶顶顶顶顶

  • dragonman (2008-10-17 14:00:07)

    这本书写的很不错，唯一的缺点是英文版的。

  • OSTINACM (2008-10-17 23:07:06)

    都是卖钱的，太可惜了

  • dragonman (2008-10-27 09:26:45)

    楼上的兄弟，有点武断了吧！
    除了第一部分收了点钱以外，其余4部分都没有收钱。但网站无论发帖者对附件是否收费，只要你下载，网站就收钱。所以，其余4部分的钱不是我收的，是论坛收的。

  • sgsun (2008-10-27 16:52:59)

    laji

  • sholo (2008-10-29 10:42:09)

    谢谢啊啊啊啊

  • fisnow (2008-10-29 21:46:15)

    Nice
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