UltraEdit 的VHDL 高亮

}n/E/K9A0E,Y#]I0将以下文本加到Ultraedit 的wordfile.txt中，即可实现VHDL高亮

C0y+HictX0 EDA中国门户网站k P9otTJ&d

/L15"VHDL" Line Comment = -- Nocase String Chars = " File Extensions = VHD VHO VHDL
r:Uu)u ?X2c'w0/Delimiters = ; ( )'<>=:+/-*|&,EDA中国门户网站XG}jxun
/Indent Strings = "entity" "architecture" "component" "begin" "(" "if" "case" "elsif" "else" "when"

b k;N Cm9W0/Unindent Strings = "end" "else" "elsif"EDA中国门户网站&_*q4F2mmoN'Tc]&o
/Open Fold Strings = "(" "process" "component" "entity" "architecture"
AsZ@#m0/Close Fold Strings = ")" "end process" "end component" "end entity" "end architecture"
.o5B1n:Ga7`UY [*W0/Function String = "%[ ^t]++^(*: process^)"EDA中国门户网站(N%pZJ%_*Q
/Function String 1 = "%[ ^t]++^(entity *^) is"
_\(cL}$NM{0a0/Function String 2 = "%[ ^t]++^(architecture *^) of"
br#m)V+]9uL5C0/Function String 3 = "%[ ^t]++^([a-zA-Z_0-9^t]+:[ a-zA-Z_0-9^t]+^)*%*map"
B&UNv%m t
A0/Function String 4 = "%[ ^t]++^(---[a-zA-Z_0-9^t*#=+^- ]+^)"EDA中国门户网站r$lq)H0^ }oR
 
VN^3B:CW_Cua0/C1"VHDL reserved words"
%qt uB3ic
[3YH+h0abs access after alias all and architecture array assert attributeEDA中国门户网站/|Yu2dkm"X*b^
begin block body buffer busEDA中国门户网站`N hX$e7Sn
jxf
case component configuration constantEDA中国门户网站[^7_KO
disconnect downtoEDA中国门户网站c7DO*p/vT`0^{
else elsif end entity exitEDA中国门户网站B8r r%C o
file for functionEDA中国门户网站:r$Pt+?0kCo.h3rb
generate generic group guardedEDA中国门户网站lO%a!n[1f$?+K1g{ @d
if impure in inertial inout is
'p~(Msu9rD^4Z&a0label library linkage literal loop
"~5@1iW;v&`g0map mod EDA中国门户网站4l*kwqTm4ger
nand new next nor not nullEDA中国门户网站aK(o)ME$Bv{
of on open or others outEDA中国门户网站D,Ul [)H4@T g!@
package port postponed procedure process pureEDA中国门户网站-m[L$D,L6k9H?
range record register reject rem report return rol rorEDA中国门户网站H
{g#Z;s#n]
select severity signal shared sla sll sra srl subtypeEDA中国门户网站1sv6_7n1KP)f'g
then to transport type
e6W'r4H+?%E@0unaffected untis until use
2z.J [~ R0variableEDA中国门户网站OQ$J f nQ
wait when while with
RT)~1B {0xnor xor

/C2"VHDL attributes"EDA中国门户网站
\$\J-|k)Ko
HyHzc
active ascending ascending EDA中国门户网站?$P!Oz;j2S{|
base
/G)}X`$V-s0delayed driving driving_value
+YE|tT
K0event EDA中国门户网站B#MvQ~%T
falling_edgeEDA中国门户网站8p ] Fl-Y1o
high EDA中国门户网站L J/h:q!V^
image instance_name EDA中国门户网站7r.Z'N*jk/UF"HL
last_active last_event last_value left leftof length low EDA中国门户网站vI1}6\llIt
path_name pos pred EDA中国门户网站"Cq.H%?E+Fq
quiet
(B!s9JQ%m-h!jt S0reverse_range right rightof rising_edgeEDA中国门户网站(g7BQ}YE%DFb[
simple_name stable succ EDA中国门户网站7f
vx!f-jkJt
transaction EDA中国门户网站~f3_aj\R
val valueEDA中国门户网站#~FDj:m YF}#c

dF ucD By4n0/C3"VHDL types"EDA中国门户网站2BO"N|Toh3_
bit bit_vector boolean EDA中国门户网站:I-rc.H9?^ U%kg5I
character
.mf)_6R&N"b0integer
p$u8B!UC0v7UR q0lineEDA中国门户网站5b {k K{6F
c$jV
natural
.E'~2t#z-Y0positiveEDA中国门户网站#@TQd9] r.g_
realEDA中国门户网站9s+zrX1fgg
signed std_logic std_logic_vector string
X$L3j'u~8N$F9QR0text timeEDA中国门户网站U"mMt3?!H#C*n
unsigned

y%O?6Mz*Jm0t0/C4"VHDL Procedures"EDA中国门户网站}c:Uh!A
endfileEDA中国门户网站Q/t4Qu&]d9}
file_close file_open
[:w5VB&m/t0read readlineEDA中国门户网站7W3kM9s,Aa ~ cy6eS0G
write writeline