About Black Matrix FPGA+USB Starter Kit~~~

参考设计之二：串口测试（VHDL源码顶层文件）

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-- 黑色矩阵 FPGA+USB 开发板参考设计之二：串口测试
PA4r(mf3Pl203880-- 用于测试开发板的基本功能模块，包括: 串口
U,M8fRE%z203880-- 本程序参考了KCPSM3的参考设计EDA中国门户网站*N-h f1T*A1?

} Ln/nq? QL203880--EDA中国门户网站MG2Hb+J3h
--
-- Reference design - Reference design for Black Matrix FPGA+USB Starter Kit EDA中国门户网站 ]9\m$[q8G3^^
--
#WV^ A%DL_S}f5f203880-- Email: spartan3@163.comEDA中国门户网站qft+`/n.J~
--EDA中国门户网站 H$VZRA\0g9x,DL
-- All rights reserved.
--
Dt ?)J&`/^i3P203880-- Introduction:
5MM!u8?Y?T7sJA203880--
?o:U[ f,t203880-- This design use RS232!
--
9uF&C0~;}%O)f9r7M203880-- PicoBlaze is included.EDA中国门户网站(aS7k)TQ5Iq
--EDA中国门户网站'~PW-Vl@HX
-- KCPSM3 reference design - Real Time Clock with UART communications
~&cH.AH:Ja z/X3A203880--
l0C6Dx4Z fw*Pp7_q7O203880-- Ken Chapman - Xilinx Ltd - October 2003
$]k,|7L0n!?203880--
*}/{*k4^$}1Q"C#Z?:?j203880-- The design demonstrates the following:-
;mFj i2?&f203880--           Connection of KCPSM3 to Program ROMEDA中国门户网站:IQ \8fPg
--           Connection of UART macros supplied with PicoBlaze with
i f2x3Nr rQi203880--                Baud rate generation
lD(|Ev1Ro/e203880--           Definition of input and output ports with
"S7M!d?;f:j ~203880--                Minimum decodingEDA中国门户网站bXt4a,h;bS
--                Pipelining where appropriate
8Sf!J4R I u U{203880--           Interrupt circuit with
U)YF4V|"g\203880--                Simple fixed period timer
] ztU*atX Tfm(x203880--                Automatic clearing using interrupt acknowledge from KCPSM3EDA中国门户网站Uso(l$m&m7e
--EDA中国门户网站N$_F:V,K%AJN
-- The design is set up for a 55MHz system clock and UART communications rate of 38400 baud.EDA中国门户网站gK8l_'Ri"~^3M
-- Please read design documentation to modify to your own requirements.
G.]R]0tfp{203880--EDA中国门户网站)?2TY lclC(_
------------------------------------------------------------------------------------EDA中国门户网站 A)MLr&C7_&k?
--
!lo]I M7_203880-- NOTICE:
)Y,E,nIs4cG203880--EDA中国门户网站x!k:Jd!`ny0f
-- Copyright Xilinx, Inc. 2003.   This code may be contain portions patented by other
9u5t {Y;tm:JRR~:|Ez/}203880-- third parties. By providing this core as one possible implementation of a standard,
q _2kuch?!YL203880-- Xilinx is making no representation that the provided implementation of this standard
K Pvo^8X0x6u7~203880-- is free from any claims of infringement by any third party. Xilinx expressly EDA中国门户网站VJ/T$LP9aV
-- disclaims any warranty with respect to the adequacy of the implementation, including EDA中国门户网站8s d aRL6I9j
-- but not limited to any warranty or representation that the implementation is free
!]@&eyw'B203880-- from claims of any third party. Furthermore, Xilinx is providing this core as a EDA中国门户网站|LC.Res
-- courtesy to you and suggests that you contact all third parties to obtain the
R W B!R2SXP9q203880-- necessary rights to use this implementation.EDA中国门户网站$?R!o%KWJC
--EDA中国门户网站(`!onxl:u,JqL
------------------------------------------------------------------------------------
--EDA中国门户网站8|.mxw,`'X
-- Library declarationsEDA中国门户网站L%gf OxJ y
--
jQXo mlp203880-- Standard IEEE librariesEDA中国门户网站l5n[/Q`$ln
--
~:nP-}#[w`%h+Sw203880library IEEE;EDA中国门户网站Lc v~*@4ry
use IEEE.STD_LOGIC_1164.ALL;EDA中国门户网站NR v$g]IW!C!Y
use IEEE.STD_LOGIC_ARITH.ALL;
^,Kq$A(M203880use IEEE.STD_LOGIC_UNSIGNED.ALL;
\m2]*f8I*V'C;b203880--
M[jNg@Q203880------------------------------------------------------------------------------------EDA中国门户网站 Cx2D$^%[
--
Oq:kaEH6VU203880--
{uree:|*|l`203880entity uart_clock is
i^e`z{J203880    Port (    tx : out std_logic;EDA中国门户网站%D/Z;ZS9EO~
              rx : in std_logic;
           alarm : out std_logic;EDA中国门户网站re3oBmeT
             clk : in std_logic);
C5?*{,{7B|*T|,v203880    end uart_clock;
ac/~8~3]!p203880--EDA中国门户网站oQ0uZu9z0|V
------------------------------------------------------------------------------------
--EDA中国门户网站}+d&E \l[!E,qs
-- Start of test architecture
v$C \n&^2^hb203880--
architecture Behavioral of uart_clock is
IY8hzmf203880--
9D8fsVU5`.G-Xt203880------------------------------------------------------------------------------------
xv'md$CA203880--
^E @GMf203880-- declaration of KCPSM3
#MH*j V'U"_5O+k"H203880--
#G*U*E4X5Ar9[\8L203880 component kcpsm3
    Port (      address : out std_logic_vector(9 downto 0);
            instruction : in std_logic_vector(17 downto 0);
Y*{oUB-O203880                port_id : out std_logic_vector(7 downto 0);
nk2R1uIJy203880           write_strobe : out std_logic;
#@DAxfy203880               out_port : out std_logic_vector(7 downto 0);
Xo-ff8M6}5E:s9|s203880            read_strobe : out std_logic;EDA中国门户网站M/a"j Nvy Ta
                in_port : in std_logic_vector(7 downto 0);
$n|0GqE\\203880              interrupt : in std_logic;
6~3a#OI`3o203880          interrupt_ack : out std_logic;
^,N|_K*OI7yU @I203880                  reset : in std_logic;
6D1jl+^u~"[203880                    clk : in std_logic);EDA中国门户网站Y7ZWZ!WW
    end component;EDA中国门户网站;a`8S0Zf+U_
--
4Ki*_w2ox [^| d203880-- declaration of program ROM
s*^Gia'ah8s!Iq203880--
i,s&r U3e^203880 component uclockEDA中国门户网站B OQ&^n@9fX@
    Port (      address : in std_logic_vector(9 downto 0);
:r_ a&g+w203880            instruction : out std_logic_vector(17 downto 0);
Q'p(l Y?a203880                    clk : in std_logic);EDA中国门户网站l0A_ ]xW?4G
    end component;
2b7UU P6w203880--EDA中国门户网站&J$mH"g{g F3^h
-- declaration of UART transmitter with integral 16 byte FIFO buffer
d9[0r6WT:k203880--
component uart_txEDA中国门户网站+x wEEV{9m R-~
    Port (            data_in : in std_logic_vector(7 downto 0);
                 write_buffer : in std_logic;
!DK/n;Mn2x7uB,X203880                 reset_buffer : in std_logic;
c]%Y$B(l203880                 en_16_x_baud : in std_logic;
l]]u|$Q203880                   serial_out : out std_logic;EDA中国门户网站\-sC DZ
                  buffer_full : out std_logic;
_i` C2U:WO203880             buffer_half_full : out std_logic;
Es ^I9A/w203880                          clk : in std_logic);EDA中国门户网站 Efg2g?Kt6G
    end component;
h"P%kd)Q(\\l203880--
%v;i["nfk;G#^'Qz-{203880-- declaration of UART Receiver with integral 16 byte FIFO buffer
:Z9u b%nNzv'^}203880--EDA中国门户网站z`Vf1K)x
component uart_rx
([.Ra9kd.Vy203880    Port (            serial_in : in std_logic;
#F+jx3W7g0h.Q203880                       data_out : out std_logic_vector(7 downto 0);
#w6e9E`*D203880                    read_buffer : in std_logic;EDA中国门户网站W*^"?h }:hQO
                   reset_buffer : in std_logic;
                   en_16_x_baud : in std_logic;
5uGN@mF6He203880            buffer_data_present : out std_logic;EDA中国门户网站3L2]3y0D,{['q
                    buffer_full : out std_logic;EDA中国门户网站-w l"W wpP5a\E
               buffer_half_full : out std_logic;
                            clk : in std_logic);
O4l:IXL0}203880 end component;EDA中国门户网站,_q+[)Dq$Dc
--EDA中国门户网站%cI#\ s!{ni
------------------------------------------------------------------------------------
6?0na$c*y)R203880--
h~J'F:LFOn203880-- Signals used to connect KCPSM3 to program ROM and I/O logic
+^:dv!sXX3^203880--EDA中国门户网站4k'EUUX0Po`P
signal address         : std_logic_vector(9 downto 0);
signal instruction     : std_logic_vector(17 downto 0);
C(Mo(r'Fp(c203880signal port_id         : std_logic_vector(7 downto 0);
@(_*?$HC_5d6p%~-c9L;Q203880signal out_port        : std_logic_vector(7 downto 0);EDA中国门户网站 ?G`w Um
signal in_port         : std_logic_vector(7 downto 0);
%@*a!j3QU d203880signal write_strobe    : std_logic;EDA中国门户网站f'W LQppq7g
signal read_strobe     : std_logic;
!}:O_+q.uap2Ry3Il203880signal interrupt       : std_logic;EDA中国门户网站3w6@we d0W-_O
signal interrupt_ack   : std_logic;EDA中国门户网站{kb^(~0j
--EDA中国门户网站a(\ D6K0n3Y [
-- Signals for connection of peripherals
--
nTk%QTP203880signal uart_status_port : std_logic_vector(7 downto 0);
4B8}#M-i4N&dU203880--
dl1}7K;UVD203880-- Signals to form. an timer generating an interrupt every microsecond
oS-R:{e(@ Z,v203880--
2T,?o"k\9r203880signal timer_count   : integer range 0 to 63 :=0;
$~b Y2w:G L w203880signal timer_pulse   : std_logic;
6M1M\.qa3h[F.Q+Tj203880--EDA中国门户网站:P$aYc HSW)t L y
-- Signals for UART connections
,la9pDFSO;D!_q1W?203880--EDA中国门户网站| O,[Z9b u*N$E4If
signal          baud_count : integer range 0 to 127 :=0;EDA中国门户网站n2o'YJ*k8X0}Ep
signal        en_16_x_baud : std_logic;
&yh;YCp*m2h203880signal       write_to_uart : std_logic;EDA中国门户网站-}_!c-]%hx9aR9z@
signal             tx_full : std_logic;
&vB*xF9]N _ L6q203880signal        tx_half_full : std_logic;
mw,V)z@pJ}203880signal      read_from_uart : std_logic;
signal             rx_data : std_logic_vector(7 downto 0);
$@5fd o!o)B203880signal     rx_data_present : std_logic;EDA中国门户网站 w-K{j+x:PL&s
signal             rx_full : std_logic;
signal        rx_half_full : std_logic;
5kZ2Sb;m*c203880--EDA中国门户网站+|*R)`w i
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
pW([6{.u6@}9u203880-- Start of circuit description
BO4ahkO#]!u203880--EDA中国门户网站v pWN]J
begin
/vl*a9Zb@.~203880 --
ms,Q;X0g'JD%o D203880 ----------------------------------------------------------------------------------------------------------------------------------
&]/OS:_ ~1v203880 -- KCPSM3 and the program memory
2j@1L'}9B&cM0X:r203880 ----------------------------------------------------------------------------------------------------------------------------------EDA中国门户网站3Y{)v7a[?l#As
--

's4T5imYRab P203880 processor: kcpsm3
hs[*prH.[203880    port map(      address => address,
A6mlt nXbp}+P203880               instruction => instruction,
:Q[4Y? _eIgo203880                   port_id => port_id,
*e\l6G&n5z@Y!dA V203880              write_strobe => write_strobe,EDA中国门户网站7z5j0b-`7M/V ]`L
                  out_port => out_port,EDA中国门户网站p(jnby|1`
               read_strobe => read_strobe,
)|+Pe{!U)R203880                   in_port => in_port,
LYJ&lFQ$O203880                 interrupt => interrupt,
]m Xd S7z&NLj203880             interrupt_ack => interrupt_ack,EDA中国门户网站u pL,~ndu!?o
                     reset => '0',EDA中国门户网站VBS8`3{
                       clk => clk);
%UF\ KY203880 EDA中国门户网站0eE}#hq
program_rom: uclock
6t oX5E&T2Y2N203880    port map(      address => address,EDA中国门户网站i5F;WW7Yb
               instruction => instruction,EDA中国门户网站+_x%kA+g/`*[HD
                       clk => clk);EDA中国门户网站LU y;s&L(o

--EDA中国门户网站&tj-RA8f
----------------------------------------------------------------------------------------------------------------------------------
-- Interrupt
6j*?b:`8S$z:]i+G203880 ----------------------------------------------------------------------------------------------------------------------------------EDA中国门户网站ZZ1dysb
--
#_'aP h0kv$T203880 --EDA中国门户网站5`|\%Gp U\
-- Interrupt is a generated once every 55 clock cycles to provide a 1us reference.
tqI7yP/an_8u203880 -- Interrupt is automatically cleared by interrupt acknowledgment from KCPSM3.EDA中国门户网站:p;} }'Tqmq,IC
--EDA中国门户网站o7n!xY^

$o+}`"tg3?4~203880 Timer: process(clk)
-A(bq.`pf)[~+F203880 beginEDA中国门户网站4v[d&\V;Vb

    if clk'event and clk='1' then
[2r`2f4[&h`+Aq203880
&E?VT1fX203880      if timer_count=54 then
/xw fw0V&Tn+N203880         timer_count <= 0;EDA中国门户网站 H4q]1{5H*Y7C^ D
         timer_pulse <= '1';EDA中国门户网站4|+O3ot W D+C;v
       elseEDA中国门户网站|7}0yS R L"x K
         timer_count <= timer_count + 1;
Kg-onj203880         timer_pulse <= '0';
/iGR5qHUX9LS f-e203880      end if;EDA中国门户网站8O'Nmvp!f H3h5G

      if interrupt_ack = '1' thenEDA中国门户网站 fW]$@-qK+C
         interrupt <= '0';
       elsif timer_pulse = '1' then
Gs)GW5jj6f,p*h:S203880         interrupt <= '1';EDA中国门户网站fG9P)U!F(Y*?
        else
         interrupt <= interrupt;EDA中国门户网站k`jby8_.d
      end if;
2}l O3Y;L7n2fk203880
m ]u^j v@7iF203880    end if;
2W4c5Me X#y9wr203880    EDA中国门户网站3]n N^!x(f-Z
end process Timer;

3b2o6i"FR+BTH9t)s-m203880EDA中国门户网站&xZ'|Oxm
--EDA中国门户网站q8w;PWoN:X
----------------------------------------------------------------------------------------------------------------------------------
T3t4|&v8p%rYf203880 -- KCPSM3 input ports
----------------------------------------------------------------------------------------------------------------------------------EDA中国门户网站1Jxc/p4ibZ\
--
--EDA中国门户网站:y#T7`}[+ja
-- UART FIFO status signals to form. a bus
fK:`WR#D+t+}203880 --

uart_status_port <= "000" & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;

--EDA中国门户网站&a4v]1n,E$l
-- The inputs connect via a pipelined multiplexer
4NO&X{ [-\203880 --

input_ports: process(clk)
,E)EqIW0k|203880 begin
#LG9h+eAF2{ qpH"qL203880 if clk'event and clk='1' then

k_M#f(ks{pE203880 case port_id(0) is

f:f P$V.X0Z*]H%Y203880
\D{6U0XuQ203880        -- read UART status at address 00 hex
8kM;N$ddN203880        when '0' =>    in_port <= uart_status_port;

        -- read UART receive data at address 01 hexEDA中国门户网站`$r;J/z+fn8_
        when '1' =>    in_port <= rx_data;
'G:W%a5wLk2~C203880
^4x1p7Xi[3b2j j-a&\203880        -- Don't care used for all other addresses to ensure minimum logic implementation
c rD$jMq203880        when thers =>    in_port <= "XXXXXXXX"; EDA中国门户网站rS'^ V'_Y1G

end case;EDA中国门户网站$[wmK&@6]Z

      -- Form. read strobe for UART receiver FIFO buffer.
6]/[%w0vb [203880      -- The fact that the read strobe will occur after the actual data is read by
,Ms7I+rGr6K%L)I203880      -- the KCPSM3 is acceptable because it is really means 'I have read you'!EDA中国门户网站,mN6A#p AlR

read_from_uart <= read_strobe and port_id(0);

+qu.A-tR4p203880 end if;

end process input_ports;

r3jh,e9gK\203880
S1lC k!e8NgCJ0v2A203880 --EDA中国门户网站mW;wi2B"e*p
----------------------------------------------------------------------------------------------------------------------------------
"Y4Aj1Db7lpA203880 -- KCPSM3 output ports
%^K:t,[5du203880 ----------------------------------------------------------------------------------------------------------------------------------
9onr2Znp$g203880 --

|jDI)}203880 -- adding the output registers to the clock processor
EDA中国门户网站)@^lU/aJ8nk
output_ports: process(clk)
,~}(r*SJC%n\203880 beginEDA中国门户网站XU1T+L1`8s{

if clk'event and clk='1' thenEDA中国门户网站0l.S0}be3kn
if write_strobe='1' then

GVB`|6p203880 -- Alarm register at address 00 hex with data bit0 providing control

        if port_id(0)='0' thenEDA中国门户网站&L,d)CP A N
          alarm <= out_port(0);
"WTg!cKcS4X)D203880        end if;

-?$X.T \p$z203880 end if;

end if;

end process output_ports;

--EDA中国门户网站 x(P*G)_r9z
-- write to UART transmitter FIFO buffer at address 01 hex.EDA中国门户网站2Q#e(@@/D0id
-- This is a combinatorial decode because the FIFO is the 'port register'.EDA中国门户网站BSFi$_
--

Dn$Bd*l4Y203880 write_to_uart <= write_strobe and port_id(0);

B)A1R5qrN203880 --
----------------------------------------------------------------------------------------------------------------------------------
6_6A.CjFn203880 -- UART
{ti:T3yk"O.X5B203880 ----------------------------------------------------------------------------------------------------------------------------------
E+[}f;y.nPE%y6{203880 --EDA中国门户网站-N|,C7_ rElH)`8_
-- Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
Y8uio"m6Z%U203880 -- Each contains an embedded 16-byte FIFO buffer.EDA中国门户网站x8j|2w/a&h,kI
--

transmit: uart_tx
ToVU'P Ju:a1V203880 port map (            data_in => out_port, EDA中国门户网站I1n/`fx
                   write_buffer => write_to_uart,EDA中国门户网站 V:kL,J,@'v
                   reset_buffer => '0',
m,Z'n,F/IhXI203880                   en_16_x_baud => en_16_x_baud,
;Pk_!zSKV)u7N@&a,?203880                     serial_out => tx,EDA中国门户网站:Km*dC N(|/@2KB
                    buffer_full => tx_full,EDA中国门户网站-gKUs I-NAt;Y
               buffer_half_full => tx_half_full,
5IzJ4wmsAJR203880                            clk => clk );EDA中国门户网站3Jk kq YCf-i

~*}NzK2X3R203880 receive: uart_rxEDA中国门户网站Uo5|ihdc%w2J
port map (            serial_in => rx,
                         data_out => rx_data,
x#?7X8V(L#bAs.S203880                      read_buffer => read_from_uart,
"c"Q;BF? De203880                     reset_buffer => '0',
&}3U`3Iq#bs|203880                     en_16_x_baud => en_16_x_baud,EDA中国门户网站!@g$D]w/@6h#`V
              buffer_data_present => rx_data_present,
8FS @~njpl203880                      buffer_full => rx_full,EDA中国门户网站 Cqs+mF
                 buffer_half_full => rx_half_full,EDA中国门户网站#BNC#|q0j'sf a
                              clk => clk ); EDA中国门户网站q,|&k}]VI:xW

j#YYa.O3UQ203880 --
4HR} L?203880 -- Set baud rate to 38400 for the UART communicationsEDA中国门户网站.r"|(p/gTi.^6sT
-- Requires en_16_x_baud to be 614400Hz which is a single cycle pulse every 90 cycles at 55MHz
--
vbK3P*z)\/lMbp203880 -- NOTE : If the highest value for baud_count exceeds 127 you will need to adjust EDA中国门户网站Q7E3NQ l%MV2h
--        the range of integers in the signal declaration for baud_count.
/e7d:@_7F'J2\g {203880 --

baud_timer: process(clk)EDA中国门户网站-EpQ*b!Zs]8R
begin
"[C-eh!q2Y203880    if clk'event and clk='1' then
6t(\G8`GTr+y1`J203880      if baud_count=89 thenEDA中国门户网站1[(W|H|4YG
           baud_count <= 0;
%u"w3C+]d*kMg` h203880         en_16_x_baud <= '1';
)Q"mkYi+jN:A!f203880       else
7c0m W2wX6f(xYA203880           baud_count <= baud_count + 1;
^a Q`7^LO&z203880         en_16_x_baud <= '0';
zEr8u&c*r203880      end if;
.b rNea#j;NJ203880    end if;EDA中国门户网站;|T2b6r:@
end process baud_timer;EDA中国门户网站? M$sbZrr

----------------------------------------------------------------------------------------------------------------------------------EDA中国门户网站4mQB4ez3Z)aX5e

s7ku7X b o203880end Behavioral;

------------------------------------------------------------------------------------------------------------------------------------EDA中国门户网站(C8}D OMf
--
2w.}#^'VQ!p U,L203880-- END OF FILE uart_clock.vhd
m8S/c5BFJL"x203880--
------------------------------------------------------------------------------------------------------------------------------------

l}e'sS \G;y0Uj203880