Modelsim中VHDL仿真警告问题

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity counter_tb is
end counter_tb;

architecture Behavioral of counter_tb is
  component sim_counter
    port(clk, reset : in std_logic;
         count : out std_logic_vector(3 downto 0)
         );
  end component;
  
  signal clk : std_logic := '0';
  signal reset : std_logic := '0';
  signal count : std_logic_vector(3 downto 0);
  
  constant clk_period : time := 20ns;
  
begin
  dut : sim_counter port map(clk => clk, reset => reset, count => count);
  clk <= '1' after 30ns when clk = '0' else
            '0' after 20ns;
  reset <= '1' after 5ns;
  reset <= '0' after 5ns;
end Behavioral;


在编译后出现警告说以下几行 (Vcom-1207) An abstrct literal and an identifier must have a separator between them.
  clk <= '1' after 30ns when clk = '0' else
            '0' after 20ns;
  reset <= '1' after 5ns;
  reset <= '0' after 5ns;

请高手指教该如何解决???
谢谢