请教状态机问题

两个功能完全的模块就是向一个ram中写数据然后在读出来，一个是用if实现，另外一个用状态机实现。前一个可以实现，但是用状态机写就没有结果。请各位大侠指点指点小弟。
always @ (posedge clk)
if(!rst_n)
begin
NUM_DATA <= 0;
BUSY <= 1;
cnt512 <= 0;
wren <= 1;
rden <= 0;
r_addrR <= 0;
w_addrR <= 0;
end
else
begin
if(TRIG_ENABLE == 1)  //write sram
   begin
    cnt512 <= cnt512 + 1;
    wren <= 1;
    rden <= 0;
    w_addrR <= cnt512;
    data_to_ram <= {5'b00000,data_in[9:0]};
    r_addrR <= 0;
   end
else
begin    //read sram
  aaa <= ior_n;
  if(aaa & !ior_n)
   begin
   if(r_addrR == 511)
    r_addrR <= 0;
   else
   begin
    wren <= 0;
    rden <= 1;
    r_addrR <= r_addrR + 1;
   end
  end
end
end
//////////////////////////////////////////////////////////////////////////////////////
//下面是用状态机写的
always @ (posedge clk)
begin
case(state)
p1:
begin
  cnt512 <= cnt512 + 1;
  wren <= 1;
  rden <= 0;
  w_addrR <= cnt512;
  data_to_ram <= {5'b00000,data_in[9:0]};
  r_addrR <= 0;
  if(TRIG_ENABLE == 1)
   state <= p1;
  else
   state <= s1;
end
s1:
begin
  aaa <= ior_n;
  if(aaa & !ior_n)
  begin
   if(r_addrR == 511)
    r_addrR <= 0;
   else
   begin
    wren <= 0;
    rden <= 1;
    r_addrR <= r_addrR + 1;
   end
  end
  if(TRIG_ENABLE == 1)
   state <= p1;
  else
   state <= s1;
end
default:
begin
  state <=1'bx;
end
endcase
end