How to turn every FPGA LVDS pair into a complete SERDES solution

In fact, I was so excited about theALLconcept that I decided to pen this brief technology introduction/backgrounder. Bryan promises that Align will follow this with a full-up "How To" article in the not-so-distant future (after the "proof-in-silicon" technology demonstration that is currently planned for sometime in Q4 2007).

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Before we pull the veils asunder and unveil the mystery of the Align Lock Loop (ALL), let's quickly review a few particularly pertinent points. Let's start with the fact that the ideal I/O solution will exhibit the following characteristics:

• Minimum pin count
• No clock to distribute
• A single clock domain
• Flexibility
• Ease-of-use
• Inexpensive

With regard to the last point, we mean inexpensive in terms of dollars, silicon area, power consumption, and complexity. Now let's consider the fact that – from one point of view – FPGAs come in three main flavors (categories):

• Cheap (for example, the Cyclone/Spartan families)
• Expensive (for example, the Stratix/Virtex families)
• Very Expensive (for example, the StratixGX/VirtexPro families)

Of course, there are variations in a variety of resources associated with the various members of the different FPGA families, but overall it's fair to generalize the little rascals as follows:

• Memory (hundreds of thousands to millions of bits)
• Logic Elements (tens to hundreds of thousands)
• I/Os (hundreds to thousands)
• DSP blocks (hundreds)
• PLLs (a dozen at most)
• CDRs (a handful at most)

The bottom line is that the inclusion of PLLs and CDRs are a key differentiator when it comes to separating FPGAs into our Cheap, Expensive, and Very Expensive categories. And so we come to the concept of the Align Lock Loop (ALL), which doesn't require a PLL or CDR in the FPGA. In order to understand how this works, consider the scenario illustrated inFig 11.

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11. Align Lock Loop (single slave device).

Now, it's very important to note that the fact that the CDR block is shown as being small as compared to the ALL function is a fiction that is used only to illustrate the way in which things hang together. In reality, the ALL logic is a small fraction of the CDR function. As usual, the ALL in the master FPGA would be implemented using programmable fabric, while the ALL in the slave would be realized as hard-wired logic.

The idea is that when the system is first powered up, the master initiates a training sequence in which it transmits a series of symbols (observe that the master requires neither a PLL nor a CDR). The slave uses its CDR to recover the clock and data; the data is passed through a phase adjuster block; and the data is then transmitted back to the master chip.

The masterchipnow introduces control codes into the data stream, where these codes are used by the phase adjuster block in the slave device to modify the phase relationship of the data it returns to the master. Eventually everything is fully synchronized, at which point the training session (which requires less than a microsecond) is terminated and the slave device can start to transmit real data back to the master.

Another interesting point is that each slave device can use its own "natural encoding" scheme. In the case of a 12-bit ADC, for example, the hard-wired ALL/CDR combo could be created in such a way as to use a 12b/14b encoding approach. The fact that the ALL in the FPGA master is fully implemented in programmable fabric means that it is "protocol agnostic" and can be configured to use any required encoding scenario.

Furthermore, the fact that the master FPGA requires neither a PLL nor a CDR means that lower-cost FPGA devices can now be used. Adding additional slave chips simply requires new ALL soft functions to be programmed into the FPGA. Furthermore, all of the slave devices can be adjusted so as to result in the FPGA seeing a single clock domain.

Of course, with bandwidths ranging from 300 mega-bits-per second to 1.5 gigabits-per-second, a single ALL channel has less bandwidth than a corresponding SERDES lane. However, designers can use any LVDS pair to implement an ALL channel, and multiple channels can be combined to increase the overall bandwidth.

SummaryEDA中国门户网站4C%Pi*w I
Personally, I think that the ALL concept is an incredibly exciting idea. Of course, one consideration is that the manufactures of devices such as ADCs (orIPproviders supplying the CDR functions that are used in these devices) have to be convinced that it is worth their while.

Now, if I were in the business of supplying ADC chips, I could care less whether the users of my chips are buying cheap FPGAs or expensive ones. What I do care about is what my competitors are doing. Let's suppose that one of my competitors decides to add the relatively small amount of logic required to implement an ALL into their devices. The fact that the ALL functionality can be enabled/disabled means that my competitor's devices can now be used in both conventional designs and in ALL-based systems.

In this case, I think my competitor will soon be selling a lot of components to system engineers who wish to use low-cost FPGAs ... at which time I will become VERY interested in incorporating ALL technology into my devices.

Keeping this in mind, I will be watching the ongoing development of ALL technology with an "eagle eye".