简单 RAM 代码示例
-- 16 字节的 RAM 设计
-- VHDL 语言与FPGA 设计- 基于PROTEL dxp开发平台 p348
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram16x8 is
port(clk : in std_logic;
address : in std_logic_vector(3 downto 0); -- 16=2**4
csbar,oebar,webar :in std_logic;
data : inout std_logic_vector(7 downto 0));
end ram16x8;
--------------------------------------------------
architecture rtl of ram16x8 is
begin
process(address,csbar,oebar,webar,data,clk)
type ram_array is array (0 to 15) of bit_vector(7 downto 0);
variable index:integer := 0;
variable ram_store : ram_array; -- 定义一个存储体
begin
if clk'event and clk='1' then
if csbar='0' then
index := 0; -- 计算地址（整数）,一定为变量
for i in address'range loop -- for i in 0 to 15 loop
if address(i)='1' then
index := index+2**i;
end if;
end loop;
end if;
if webar='1' then
-- 当'写'脉冲的上升沿到来的时才能进行写RAM操作
ram_store(index) := to_bitvector(data);
elsif ebar='0' then
data <= to_stdlogicvector(ram_store(index));
else
data <= (others=>'Z');
end if;
end if;
end process;
end rtl;
