Should You Reuse RTL?

原文见FPGAandStructuredASICJournal

• Cutting & pasting a single routine or function
• Copying existing simple blocks or modules into the new design.
• Coping large design blocks and building around them with new blocks
• Building around an existing platform by adding a few new blocks.

Determine design Integrity

Design integrity fundamentally means that all the code is complete and ready for simulation. When you faced with a directory of data to recycle, you need to figure out what files are necessary and which ones can be discarded for their new project. Finally, you need to figure out the integrity of the remaining files.

Dealing with Missing Files

·       Include or package files                 

·       Referenced technology instances

·       Referenced blocks

 Dealing with Errors

·       Missing Files

·       Tool Settings

·       Actual errors

Understanding the design

One good way to understands what the code does is using a tool that allows visualization techniques. With this way, if a missing design block is found, it can be quickly created.

Determine Code Quality

·       Coding practices

o      The potential functional errors. e.g. incomplete sensitivity list.

·       Downstream tool issues

§        Check the violations that indicate the code will have problems in a specific tool in your tool chain. e.g. the code contains elements that cannot be synthesized.

·       Style.

o      Check violations due to how code physically appears in the file. e.g. a good/unify coding style is quite good for the reuse and future project.

Establish Design Validity

·       Does a testbench exist?

o      Designers can try to get by without a testbench for the code block and just use the high-level testbench for the entire project, but it is not advised.

·       Does the testbench contain many tests?

o      If not, testing routines must be added to ensure acceptable coverage.

·       If code converage can be analyzed, does the testbench exercise the entire design?

o      The impact can be major if the coverage is not acceptable or if the appropriate code needs to be inserted to instrument for functional coverage.

·       Do the testbench and the design contain assertions?

o      Assertions allow designers to pin-point the logic and the exact time a violation occurred. The impact is minimal if the code has quality assertions. The impact can be major if debugging time increases due to lake this.

·       Are there simulation errors?

·       How much time do you actually spend simulating?

o      However, as code is modified, it has to be re-simulated.