主要从事0.13um, 90nm,65nm 的 Soc 设计服务和ip 核研发。 招聘一名 soc后端设计工程师.
Requirement:
(1) Bachelor's degree in Electrical Engineering or other related engineering degree. 3+ years of Soc backend experiences
(2) a proven track record in synthesis and/or place and route
(3) Experience with Synopsys design tools (IC compiler).
(4) Experience in LVS/DRC tools is a must.
(5) English language skill is necessary.
(6) Perform the backend process with a minimal amount of supervision and be capable of working in a team environment.
(7) Location: xi'an
Job Description and Responsibilities:
floor planning
placement
test logic insertion
clock tree synthesis
routing
post-route timing and crosstalk noise analysis and fixing
physical design verification using Mentor graphics Calibre.
有意者请将简历发到:qianliu27@hotmail.com



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huxinhuwei (2008-9-11 16:13:27)
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feiying_cq (2008-9-17 22:47:03)