刚学Modelsim这个仿真软件，碰到一点问题，希望各位大虾给以指点，在此先行谢过。
昨天下了一个教程，按上面的说法VHDL是没问题的。现在我用同样的方法来仿真Verilog，结果是在我进编译和vsim testbench文件后，在signals窗口中什么信号也没有看见。
一个简单的计数器测试文件（该软件自带），如下 ：
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO ****** TERMS.
//
module test_counter;
reg clk, rst;
wire [7:0] count;
counter #(5,10) dut (count,clk,rst);
initial // Clock generator
begin
clk = 0;
#10 forever #10 clk = !clk;
end
initial // Test stimulus
begin
rst = 0;
#5 rst = 1;
#4 rst = 0;
#50000 $stop;
end
initial
$monitor($stime,, rst,, clk,,, count);
endmodule
另外计数器也是自带的，如下：
//
// Copyright 2006 Mentor Graphics Corporation
//
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO ****** TERMS.
//
module counter (count, clk, rst);
output [7:0] count;
input clk, rst;
reg [7:0] count;
parameter tpd_clk_to_count = 1;
parameter tpd_reset_to_count = 1;
function [7:0] increment;
input [7:0] val;
reg [3:0] i;
reg carry;
begin
increment = val;
carry = 1'b1;
/*
* Exit this loop when carry == zero, OR all bits processed
*/
for (i = 4'b0; ((carry == 4'b1) || (i <= 7)); i = i+ 4'b1)
begin
increment = val ^ carry;
carry = val & carry;
end
end
endfunction
/*****************************************************************
* The following always block was changed to make it synthesizable.
always @ (posedge clk or posedge rst)
if (rst)
count = #tpd_reset_to_count 8'h00;
else
count <= #tpd_clk_to_count increment(count);
******************************************************************/
always @ (posedge clk or posedge rst)
if (rst)
count = 8'h00;
else
count <= count + 8'h01;
endmodule
