美资半导体公司招聘以下职位

[size=7.5pt]Location : [size=7.5pt]Shanghai[size=7.5pt]

[size=7.5pt]Short Description :

[size=7.5pt]Analog circuit design and simulation

[size=7.5pt]Key Responsibilities :

• [size=7.5pt]Analog circuit design for high speed SERDES
• [size=7.5pt]Top level simulation on digital/analog mixed design.

[size=7.5pt]Skill set :[size=7.5pt]

• [size=7.5pt]Master/Bachelor Degree, with 3 or more years working experience[size=7.5pt];[size=7.5pt]
• [size=7.5pt]In depth knowledge of CMOS circuit schematics, simulation, layout.[size=7.5pt]
• [size=7.5pt]Experience in EDA tools use.
• [size=7.5pt]Knowledge in PLL, VGA, PRML, ADC, DAC, Equalizer, LPF etc.
• [size=7.5pt]Experience in board level circuit debug.
• [size=7.5pt]Good communication skills[size=7.5pt]
• [size=7.5pt]Experience in High speed SERDES design is preferred.[size=7.5pt]

[size=7.5pt]Mind set :[size=7.5pt]

• [size=7.5pt]Team worker
• [size=7.5pt]Quality minded
• [size=7.5pt]Self motivator
• [size=7.5pt]Kind and friendly personality
• [size=7.5pt]Curious about new techniques, technologies and tools
• [size=7.5pt]Fast learner
• [size=7.5pt]Creative & innovative

Title: Senior System Engineer (2)-Shanghai

[size=7.5pt]Location : [size=7.5pt]Shanghai[size=7.5pt]

[size=7.5pt]Short Description :

[size=7.5pt]Develop system simulation environment

[size=7.5pt]Key Responsibilities :

• [size=7.5pt]Architecture design of circuit
• [size=7.5pt]System verification

[size=7.5pt]Skill set :[size=7.5pt]

• [size=7.5pt]Master Degree above, with 3 or more years working experience[size=7.5pt];[size=7.5pt]
• [size=7.5pt]In depth knowledge of mixed signal simulation, system simulation tools, behavior model design[size=7.5pt]
• [size=7.5pt]Knowledge in communication standard.
• [size=7.5pt]Experience in Ethernet Giga PHY is preferred.
• [size=7.5pt]Good communication skills[size=7.5pt]

[size=7.5pt]Mind set :[size=7.5pt]

• [size=7.5pt]Team worker
• [size=7.5pt]Quality minded
• [size=7.5pt]Self motivator
• [size=7.5pt]Kind and friendly personality
• [size=7.5pt]Curious about new techniques, technologies and tools
• [size=7.5pt]Fast learner
• [size=7.5pt]Creative & innovative[size=7.5pt]

Title: Senior Digital IC Design/Verification Engineer-Shanghai

[size=7.5pt]Location : [size=7.5pt]Shanghai[size=7.5pt]

[size=7.5pt]Short Description :

[size=7.5pt]Digital IC Design and verification

[size=7.5pt]Key Responsibilities :

• [size=7.5pt]System Level Digital IC Design;
• [size=7.5pt]Devise system verification solution
• [size=7.5pt]Develop product specs and design specs
• [size=7.5pt]Design simulation/verification environment
• [size=7.5pt]Perform IC module Design, System Simulation, and FPGA Verification
• [size=7.5pt]Help Layout, Co-operating with Layout
• [size=7.5pt]Perform circuit optimization and debug

[size=7.5pt]Skill set :[size=7.5pt]

• [size=7.5pt]MSEE or higher, over 3 years IC design Background;[size=7.5pt]
• [size=7.5pt]Good skills in Xilinx, Altera, Synopsys, and Cadence EDA software[size=7.5pt]
• [size=7.5pt]Experienced in system design, or IC/FPGA design/verification;[size=7.5pt]
• [size=7.5pt]Strong background in Communication or PC field.[size=7.5pt]
• [size=7.5pt]Experience in protocol on TCP/IP, PCI-Express, SATA is preferred[size=7.5pt]
• [size=7.5pt]Good communication skills[size=7.5pt]

[size=7.5pt]Mind set :[size=7.5pt]

• [size=7.5pt]Team worker
• [size=7.5pt]Quality minded
• [size=7.5pt]Self motivator
• [size=7.5pt]Kind and friendly personality
• [size=7.5pt]Curious about new techniques, technologies and tools
• [size=7.5pt]Fast learner
• [size=7.5pt]Creative & innovative

[size=7.5pt]Location : [size=7.5pt]Shanghai[size=7.5pt]

[size=7.5pt]Short Description :

[size=7.5pt]Backend implementation and verification

[size=7.5pt]Key Responsibilities :

• [size=7.5pt]Timing closure/STA or
• [size=7.5pt]Crosstalk analysis or[size=7.5pt]
• [size=7.5pt]DFT including scan test, MBIST, boundary scan or
• [size=7.5pt]Physical Check

[size=7.5pt]Skill set :[size=7.5pt]

• [size=7.5pt]MSEE or higher, over 3 years back-end flow Background[size=7.5pt]
• [size=7.5pt]0.13um process and below, 1M gates backend design experience required[size=7.5pt]
• [size=7.5pt]Familiar with milestones in back-end flow[size=7.5pt]
• [size=7.5pt]Good skills in back-end EDA tools.[size=7.5pt]
• [size=7.5pt]Experienced in IP integration;[size=7.5pt]
• [size=7.5pt]Good communication skills/team work[size=7.5pt]

[size=7.5pt]Mind set :[size=7.5pt]

• [size=7.5pt]Team worker
• [size=7.5pt]Quality minded
• [size=7.5pt]Self motivator
• [size=7.5pt]Kind and friendly personality
• [size=7.5pt]Curious about new techniques, technologies and tools
• [size=7.5pt]Fast learner
• [size=7.5pt]Strong sense of responsibility[size=7.5pt]

Title: Senior Servo Engineer (5)-Shanghai

[size=7.5pt]Location : [size=7.5pt]Shanghai[size=7.5pt]

[size=7.5pt]Short Description :

[size=7.5pt]Develop the reference system for blue ray Front End DVD-SoC

[size=7.5pt]Key Responsibilities :

• [size=7.5pt]Design system/servo firmware
• [size=7.5pt]Cooperate with IC Design team for system integration & chip test

[size=7.5pt]Skill set :[size=7.5pt]

• [size=7.5pt]Master/Bachelor Degree, with 3 or more years working experience[size=7.5pt];[size=7.5pt]
• [size=7.5pt]In depth knowledge of optical storage system[size=7.5pt]
• [size=7.5pt]Experience in firmware for optical storage.
• [size=7.5pt]Knowledge in embedded system development.
• [size=7.5pt]Experience in ATAPI protocol, servo tuning is preferred.
• [size=7.5pt]Good communication skills[size=7.5pt]

[size=7.5pt]Mind set :[size=7.5pt]

• [size=7.5pt]Team worker
• [size=7.5pt]Quality minded
• [size=7.5pt]Self motivator
• [size=7.5pt]Kind and friendly personality
• [size=7.5pt]Curious about new techniques, technologies and tools
• [size=7.5pt]Fast learner
• [size=7.5pt]Creative & innovative[size=7.5pt]

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[size=7.5pt]大家可发送简历到：xinjihr_cn@126.com

[size=7.5pt]或者联系：mouhuitou@hotmail.com

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