我在自己练习写的一个LCD驱动的程序,但是在仿真的时候出现了问题。先贴代码
module lcd_driver (clk,reset,lcdda,lcdrw,lcden,data);
parameter [2:0] ST_DLNF=3'b000,ST_CURSOR=3'b001,
ST_DCB=3'b010,ST_CGRAM=3'b011,
WRITE_CGRAM=3'b100,SET_DDRAM=3'b101,
WRITE_DATA=3'b110;
input clk,reset;
output lcdda,lcdrw,lcden;
output [7:0]data;
reg [2:0]cstate,nstate;
reg [7:0]ram [2:0];
reg lcdda,lcdrw;
reg [7:0]data;
reg [2:0] cnt;
assign lcden=clk;
initial
begin
ram[0]=8'h08;
ram[1]=8'h0f;
ram[2]=8'h12;
ram[3]=8'h0f;
ram[4]=8'h0a;
ram[5]=8'h0f;
ram[6]=8'h02;
ram[7]=8'h02;
lcdda=1'b0;
lcdrw=1'b0;
cnt=3'b000;
end
always @(posedge clk or negedge reset)
begin
if(reset==1'b0)
begin
cstate<=ST_DLNF;
end
else
cstate<=nstate;
end
always @(posedge clk)
begin
case(cstate)
ST_DLNF:begin
data<=8'h3c;
nstate<=ST_CURSOR;
end
ST_CURSOR:begin
data<=8'h06;
nstate<=ST_DCB;
end
ST_DCB:begin
data<=8'h0f;
nstate<=ST_CGRAM;
end
ST_CGRAM:begin
data<=8'h40;
nstate<=WRITE_CGRAM;
end
WRITE_CGRAM:begin
lcdda<=1'b1;
data<=ram[cnt];
cnt<=cnt+1;
if(cnt==3'b111)
begin
nstate<=SET_DDRAM;
cnt<=3'b000;
end
else
nstate<=WRITE_CGRAM;
end
SET_DDRAM:begin
data<=8'h80;
nstate<=WRITE_DATA;
end
WRITE_DATA:begin
data<=8'h00;
lcdda<=1'b1;
nstate<=ST_DLNF;
end
default:nstate<=ST_DLNF;
endcase
end
endmodule
我在Initial中首先对一个存储器赋了初值,但是在仿真的时候却发现里面没有值。而且仿真的时候出现了下面的警告
Warning: Verilog HDL unsupported feature warning at lcd_driver.v(29): Initial Construct is not supported and will be ignored
请大家指点一下应该怎么去改这个程序。
是不是Initial语句应该仿真写testbench的时候



最新回复
shaweikang1984 (2008-10-06 21:49:46)
zhouhong0809 (2008-10-06 22:00:15)
mshph (2008-10-06 22:30:12)