请教：altpll综合后仿真和时序仿真不出结果？

我在quartus中调用了altera的megafunciton：altpll，将20M频率倍到40M，然后在modelsim中利用调用时生成的*.v文件和自己编写的testbench文件新建了工程并完成了综合前的仿真，结果正确。但是在进行综合后仿真（利用quartus生成的*.vo文件和自己编写的testbench文件新建工程）以及时序仿真（在前者基础上加入了sdf文件）却没有结果出来，而在装载设计时并没有报什么错，以下是装载设计后的信息：
vsim -L F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver -sdftyp {/dut=F:/zy/work/synplify project/modelsim_project/PLL_testbench/test_postPR/mypll_v.sdo} work.test_mypll
# vsim -L F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver -sdftyp {/dut=F:/zy/work/synplify project/modelsim_project/PLL_testbench/test_postPR/mypll_v.sdo} work.test_mypll
# Loading work.test_mypll
# Loading work.mypll
# ** Warning: (vsim-3010) [TSCALE] - Module 'mypll' has a `timescale directive in effect, but previous modules do not.
#         Region: /test_mypll/dut
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_io
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_mux21
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_dffe
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_asynch_io
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_pll
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_pll_reg
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_m_cntr
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_n_cntr
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_scale_cntr
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_clkctrl
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_mux41
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.cycloneii_ena_reg
# Loading F:/zy/work/modelsim_library/altera_lib/verilog/cycloneii_ver.CYCLONEII_PRIM_DFFE
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Region: /test_mypll  File: F:/zy/work/synplify project/modelsim_project/PLL_testbench/test_postPR/test_mypll.v
之后我便运行（按F9），结果波形如下图，没有结果