最新更新主题

月度关注热点

上海恒原微电子招聘（详细版）

字体: 小 中 大 | 打印 发表于: 2008-7-22 19:38    作者: diploma    来源: EDA中国门户网站

上海恒原微电子  http://www.panovel.com/

职位名称：物理层ASIC设计工程师
1．
职责：
(1)
与‘物理层系统工作组’合作提出物理层ASIC框图架构；
(2)
物理层算法的ASIC实现；
(3)
与‘MAC工作组’和‘固件组’合作完成‘物理层-MAC’接口；
(4)
物理层的FPGA验证和排错。
2．
资格：
(1)
OFDM物理层实现的直接工作经验；
(2)
OFDM物理层优化和排错的直接工作经验；
(3)
在ASIC设计流程，包括时序等方面有丰富经验。
3．
优先考虑:
有FPGA实现，无线通信IC设计经验者；硕士或以上学历。



Position title: Phy ASIC Engineer
1．
Responsibilities:
(1)
Work with PHY system group to come up with PHY ASIC block architecture;
(2)
ASIC implementation of PHY algorithm;
(3)
Work with MAC and Firmware groups for PHY-MAC interface;
(4)
FPGA validation and debugging of PHY algorithms;
2．Qualification:
(1)
Hands on experience on OFDM PHY implementation;
(2)
Hands on experience on OFDM PHY optimization and debugging;
(3)
Solid experience on ASIC flow, including timing closure.
3．
Priority:

FPGA mapping capability;

Wireless communication IC design experience;

MS and higher.
我也来说两句 查看全部回复

最新回复

  • diploma (2008-7-22 19:40:26)

    职位名称：MAC ASIC design engineer

    Solid experience in SoC design
    Solid experience in ASIC flow
    MAC experience preferred, including scheduling and queue management
    ARQ implementation experience preferred
    Memory management experience preferred
    AMBA bus experience preferred
    MS with 3 plus years experience

  • diploma (2008-7-22 19:41:23)

    Senior ASIC Verification Engineer

    Required:

    -        Minimum of 3 years ASIC verification experience in a product development environment with proven ASIC design verification skills
    -        Experience in using event-driven simulators like VCS
    -        Fluent in Verilog for design verification
    -        Experience in writing testbench using System Verilog
    -        Knowledge of peripheral IP intergration (PCI, USB2.0, PCI)
    -        Knowledge of AMBA/AHB/DMA
    -        Experience with one or more scripting languages: Perl, TCL, Shell
    -        Superior debugging skills for large ASIC designs
    -        Strong written and verbal communication skills

    Required Degree: MS
    Preferred Major: Electrical Engineering or related discipline

    Job Description :  Job Responsibilities

    -        Working within an ASIC design team to develop reusable block-level and ASIC testbenches using high-level verification language (System Verilog).
    -        Develop new ASIC verification environments to support ASIC development.
    -        Review RTL architectural and implementation specifications.
    -        Create stimulus drivers, monitors, dataflow models, and test plans to verify function and performance of advanced SOC ASICs.
    -        Define and implement code/functional coverage plans.
    -        Develop testing and regression methodologies for new verification flow.
    -        Incorporate reusability into all aspects of the verification environment.
    -        Develop/maintain/enhance environment tools/scripts/makefiles.

  • diploma (2008-7-22 19:41:52)

    Senior Digital Back-end Design Engineer

    Required:
    -        3-5 years experience in backend design flow with proven SOC tapeout experience.
    -        Expertise in floorplan, place and routing, signal integrity, power analysis, CTS, DFT, ECO, DRC, LVS.
    -        Experienced in Synopsys/Cadence) physical design tools and flows.
    -        Experienced in Mentor’s Calibre flow for DRC/ERC/LVS/Antenna flow.
    -        Strong timing analysis capabilities.
    -        Experience with one or more scripting languages (Perl, TCL, Shell) to automate physical design flow.
    -        Good analytical and debugging skills.
    -        Strong written and verbal communication skills.

    Required Degree: BS
    Preferred Degree: MS
    Preferred Major: Electrical Engineering or related discipline

    Job Responsibilities

    -        Responsible for developing and verifying complex digital designs with emphasis on backend tasks, including Floorplan, power planning and routing, CTS, PnR, RC extraction, ECO, DRC, LVS.
    -        Work with RTL designers to optimize timing/area/power of the physical design implementation and perform static timing analysis.

  • diploma (2008-7-22 19:43:35)

    职位名称：Senior High Speed Digital Filter Design Engineer

    Solid experience in high speed digital design with custom flow
    Solid experience in timing closure with Spice simulation
    Deep knowledge in CMOS digital design, with hands-on experience on layout and post layout
    simulation
    Good knowledge of filter design

    Good knowledge of multirate signal processing

  • diploma (2008-7-22 19:44:57)

    职位名称：周边功能模块ASIC设计工程师
    　　1． 职责
    　　(1) 评估不同供应商提供的周边功能模块的性能和价格；
    　　(2) 验证这些功能模块；
    　　(3) 在UWB片上系统(SoC)上集成功能模块；
    　　(4) 通过顶层测试平台仿真验证功能模块。
    　　2． 资格
    　　(1) 具有外围功能模块（PCI，USB和SDIO）集成、验证和排错的直接工作经验；
    　　(2) 具有ASIC设计流程的丰富经验。
    　　3． 优先考虑:
    　　具有FPGA经验者；硕士或以上学位。

  • diploma (2008-7-22 19:46:38)

    对以上职位感兴趣且符合以上职位要求者，请发送中英文简历至：
    wenping.xie@panovel.com

  • steed (2008-7-22 22:27:29)

    你小子转的倒挺快的,哈哈

  • ic_crazy (2008-7-23 09:18:43)

    QUOTE:

    原帖由 diploma 于 2008-7-22 19:46 发表
    对以上职位感兴趣且符合以上职位要求者，请发送中英文简历至：
    wenping.xie@panovel.com
    你是不是猎头? 怎么看到你发过好几个公司的招聘信息?

  • sunkaihong (2008-7-23 19:19:21)

    upupup

  • tspen (2008-7-23 19:30:47)

    之前投过简历的还用发么

  • diploma (2008-7-23 20:36:44)

    投过简历的不用再投了，前面的简历都已经转给各个技术部门了，
    具体的事情等待技术部门安排！谢谢关注。

  • blackhyw (2008-7-24 10:32:42)

    但管理团队的能力经验是个问题..........

  • xwq8204 (2008-7-27 15:11:10)

    赫赫，在这里发布招聘信息的大都是猎头？
查看全部回复 我也来说两句