modelsim 仿真模拟显示

module couter(clk,clear,load,d,q);
    input clk,clear,load;
    input [3:0]d;
    output [3:0]q;
    reg [3:0]q;
    always @(posedge clk)
       begin
           if(!clear)
             q<=0;
           else if(!load)
                   q<=d;
                 else if(q==9)
                        q<=0;
                      else
                        q<=q+1;
       end               
endmodule
对应测试代码
`timescale 1ns/1ns
module tb_counter;
reg clk,clear,load;
reg [3:0]d;
wire [3:0]q;
always #20 clk=~clk;
initial
   begin
        clk=0;
        clear=1;
        load=1;
        d=4'b1000;
        #100 clear=0;
        #40   clear=1;
        #30  load=0;
        #40   load=1;
        #20000 $stop;
  end
couter m(.clk(clk),.clear(clear),.load(load),.d(d),.q(q));
endmodule

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