Modelsim_xilinx库编译

Modelsim_xilinx库编译

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Modelsim如何编译xilinx库

Modelsim编译xilinx库的步骤
1、打开ISE，到Edit->Preference->Integrated ToolS将位置定位到modulesim安装目录下的win32

2、在d:\ModelTech_6.2b\下建立新目录，并命名为Xilinx_Lib

3、到DOS环境下(命令行)，并切到ISE安装目录下\Bin\Nt(dir D:\xilinx\bin\nt)

4、输入命令 compxlib -s mti_se -f all -l all -o d:\ModelTech_6.2b\xilinx_lib -p d:\ModelTech_6.2b\Win32。
编译得到仿真库。(-o d:\ModelTech_6.2b\xilinx_lib指编译后文件的存放位置）

5、copy以下内容到安装目录下的ModelSim.ini(需要去掉只读属性)文件的[Library]下，

如果执行正常的话,以下文件应该已经自动创建..........
  ; VHDL Section
  unisim = D:/Modeltech_6.2b/xilinx_lib/unisim
  simprim = D:/Modeltech_6.2b/xilinx_lib/simprim
  xilinxcorelib = D:/Modeltech_6.2b/xilinx_lib/xilinxcorelib
  aim = D:/Modeltech_6.2b/xilinx_lib/abel/aim
  pls = D:/Modeltech_6.2b/xilinx_lib/abel/pls
  cpld = D:/Modeltech_6.2b/xilinx_lib/cpld
  ; Verilog Section
  unisims_ver = D:/Modeltech_6.2b/xilinx_lib/unisims_ver
  uni9000_ver = D:/Modeltech_6.2b/xilinx_lib/uni9000_ver
  simprims_ver = D:/Modeltech_6.2b/xilinx_lib/simprims_ver
  xilinxcorelib_ver = D:/Modeltech_6.2b/xilinx_lib/xilinxcorelib_ver
  aim_ver = D:/Modeltech_6.2b/xilinx_lib/abel_ver/aim_ver
  cpld_ver = D:/Modeltech_6.2b/xilinx_lib/cpld_ver
6、结束
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D:\Xilinx\10.1\ISE\bin\nt>compxlib -s mti_se -f all -l all -o c:\Modeltech_6.2b\
xilinx_lib -p c:\Modeltech_6.2b\Win32
XILINX = 'D:\Xilinx\10.1\ISE'
Release 10.1 - COMPXLIB K.31
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

Library Source => 'D:\Xilinx\10.1\ISE'

Compilation Mode = FAST
Scheduling library installation & compilation for all architectures
MTI => Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006

--> Installing Xilinx smartmodel library .....
    > Environment variable LMC_HOME = 'D:\Xilinx\10.1\ISE\smartmodel\nt\installe
d_nt'
    > The installation directory pointed by LMC_HOME doesn't exist.
    > Creating this installation directory: D:\Xilinx\10.1\ISE\smartmodel\nt\ins
talled_nt ...
    > Extracting model names from 'D:\Xilinx\10.1\ISE\smartmodel\nt\image\sl_toc
.dat'
    > Creating 'model.list' at current directory

Library Image directory : 'D:\Xilinx\10.1\ISE\smartmodel\nt\image'
Installation directory : 'D:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt'
Running installer......

Synopsys/Logic Modeling sl_admin
Copyright (c) 1984-2000 Synopsys Inc. ALL RIGHTS RESERVED
Version: 02042

Reading Media
Checking user selections
Loading models....
Loading model: dcc_fpgacore_swift, version: 03403, platform. pcnt
Loading model: emac_swift, version: 02023, platform. pcnt
Loading model: glogic_adv_swift, version: 02005, platform. pcnt
Loading model: glogic_swift, version: 05002, platform. pcnt
Loading model: gt10_swift, version: 03222, platform. pcnt
Loading model: gt11_swift, version: 02017, platform. pcnt
Loading model: gt_swift, version: 02603, platform. pcnt
Loading model: gtp_dual_swift, version: 01011, platform. pcnt
Loading model: gtx_dual_swift, version: 01006, platform. pcnt
Loading model: pcie_internal_1_1_swift, version: 01020, platform. pcnt
Loading model: ppc405_adv_swift, version: 02011, platform. pcnt
Loading model: ppc405_swift, version: 05004, platform. pcnt
Loading model: ppc440_swift, version: 01009, platform. pcnt
Loading model: temac_swift, version: 01004, platform. pcnt
Updating Configuration files
Writing: D:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt/data/pcnt.lmc
Updating Library Versioned links
Updating Documentation files
Updating Library cache
Install complete


Compiling Xilinx HDL Libraries for ModelSim SE Simulator
Language => verilog, vhdl
Backing up setup files if any...
Output directory => 'c:\Modeltech_6.2b\xilinx_lib'

--> Compiling verilog unisim library
    > Unisim compiled to c:\Modeltech_6.2b\xilinx_lib\unisims_ver
    > Log file c:\Modeltech_6.2b\xilinx_lib\unisims_ver\cxl_unisim.log generated

    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unisims_ver]: No error(s), no warning(s)

--> Compiling verilog unimacro library
    > unimacro compiled to c:\Modeltech_6.2b\xilinx_lib\unimacro_ver
    > Log file c:\Modeltech_6.2b\xilinx_lib\unimacro_ver\cxl_unimacro.log genera
ted
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unimacro_ver]: No error(s), no warning(s)

--> Compiling verilog uni9000 library
    > Uni9000 compiled to c:\Modeltech_6.2b\xilinx_lib\uni9000_ver
    > Log file c:\Modeltech_6.2b\xilinx_lib\uni9000_ver\cxl_uni9000.log generate
d
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[uni9000_ver]: No error(s), no warning(s)

--> Compiling verilog simprim library
    > Simprim compiled to c:\Modeltech_6.2b\xilinx_lib\simprims_ver
    > Log file c:\Modeltech_6.2b\xilinx_lib\simprims_ver\cxl_simprim.log generat
ed
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[simprims_ver]: No error(s), no warning(s)

--> Compiling verilog XilinxCoreLib library
    > XilinxCoreLib compiled to c:\Modeltech_6.2b\xilinx_lib\XilinxCoreLib_ver
    > Log file c:\Modeltech_6.2b\xilinx_lib\XilinxCoreLib_ver\cxl_XilinxCoreLib.
log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[XilinxCoreLib_ver]: No error(s), 6 warning(s)
MTI => Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006

--> Compiling verilog smartmodel(unisim) library
    > unable to parse initialization file. Check if the
      file modelsim.ini is present in the current directory
      with read/write permissions
    > SWIFT Interface configuration procedure failed
    > Unisim Smart-Models compiled to c:\Modeltech_6.2b\xilinx_lib\unisims_ver
    > Log file c:\Modeltech_6.2b\xilinx_lib\unisims_ver\cxl_smartmodel.log gener
ated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[smartmodel]: No error(s), no warning(s)

--> Compiling verilog smartmodel(simprim) library
    > unable to parse initialization file. Check if the
      file modelsim.ini is present in the current directory
      with read/write permissions
    > SWIFT Interface configuration procedure failed
    > Simprim Smart-Models compiled to c:\Modeltech_6.2b\xilinx_lib\simprims_ver

    > Log file c:\Modeltech_6.2b\xilinx_lib\simprims_ver\cxl_smartmodel.log gene
rated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[smartmodel]: No error(s), no warning(s)

--> Compiling verilog abel library
    > Abel compiled to c:\Modeltech_6.2b\xilinx_lib\abel_ver
    > Log file c:\Modeltech_6.2b\xilinx_lib\abel_ver\cxl_abel.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[abel_ver]: No error(s), no warning(s)

--> Compiling verilog cpld library
    > Cpld compiled to c:\Modeltech_6.2b\xilinx_lib\cpld_ver
    > Log file c:\Modeltech_6.2b\xilinx_lib\cpld_ver\cxl_cpld.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[cpld_ver]: No error(s), no warning(s)
Output directory => 'c:\Modeltech_6.2b\xilinx_lib'

--> Compiling vhdl unisim library
    > Unisim compiled to c:\Modeltech_6.2b\xilinx_lib\unisim
    > Log file c:\Modeltech_6.2b\xilinx_lib\unisim\cxl_unisim.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unisim]: No error(s), no warning(s)

--> Compiling vhdl unimacro library
    > unimacro compiled to c:\Modeltech_6.2b\xilinx_lib\unimacro
    > Log file c:\Modeltech_6.2b\xilinx_lib\unimacro\cxl_unimacro.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unimacro]: No error(s), no warning(s)

--> Compiling vhdl simprim library
    > Simprim compiled to c:\Modeltech_6.2b\xilinx_lib\simprim
    > Log file c:\Modeltech_6.2b\xilinx_lib\simprim\cxl_simprim.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[simprim]: No error(s), no warning(s)

--> Compiling vhdl XilinxCoreLib library
    > XilinxCoreLib compiled to c:\Modeltech_6.2b\xilinx_lib\XilinxCoreLib
    > Log file c:\Modeltech_6.2b\xilinx_lib\XilinxCoreLib\cxl_XilinxCoreLib.log
generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[XilinxCoreLib]: No error(s), 3 warning(s)
MTI => Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006

--> Compiling vhdl smartmodel(unisim) library
    > unable to parse initialization file. Check if the
      file modelsim.ini is present in the current directory
      with read/write permissions
    > SWIFT Interface configuration procedure failed
    > Unisim Smart-Models compiled to c:\Modeltech_6.2b\xilinx_lib\unisim
    > Log file c:\Modeltech_6.2b\xilinx_lib\unisim\cxl_smartmodel.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[smartmodel]: No error(s), no warning(s)

--> Compiling vhdl smartmodel(simprim) library
    > unable to parse initialization file. Check if the
      file modelsim.ini is present in the current directory
      with read/write permissions
    > SWIFT Interface configuration procedure failed
    > Simprim Smart-Models compiled to c:\Modeltech_6.2b\xilinx_lib\simprim
    > Log file c:\Modeltech_6.2b\xilinx_lib\simprim\cxl_smartmodel.log generated

    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[smartmodel]: No error(s), no warning(s)

--> Compiling vhdl abel library
    > Abel compiled to c:\Modeltech_6.2b\xilinx_lib\abel
    > Log file c:\Modeltech_6.2b\xilinx_lib\abel\cxl_abel.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[abel]: No error(s), no warning(s)

--> Compiling vhdl cpld library
    > Cpld compiled to c:\Modeltech_6.2b\xilinx_lib\cpld
    > Log file c:\Modeltech_6.2b\xilinx_lib\cpld\cxl_cpld.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[cpld]: No error(s), no warning(s)



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MODELSIM中添加Xilinx的库(转)
0
推荐目前MODELSIM的过程中，很多人往往被如何添加库所迷惑。

主要是有两个原因，一个是流行的很多做法太复杂，不适合新手们使用。二是新手们在学习具体使用上有些浮躁。

对于特别复杂的做法，本文将不涉及任何一点，害怕大家犯晕。

介绍两种非常简单方便的做法：

（1）是我认为最好的（我不喜欢把最好的放在最后，怕影响大家的热情）

首先将modelsim.ini文件只读模式去掉，存档前面打对勾。
在您安装ise的目录下，进入到bin\nt目录下，例如c:\ise\bin\nt，确认有compxlib这个程序
在cmd中运行compxlib -s mti_se -f all -l all -o －dir c:\modeltech\xilinx_libs就可以了，c:\modeltech是我安装modelsim的目录，您可以作相应的更改。参数也可以按照您的要求作相应的更改。
  对于3，很多人可能犯点糊涂，即使使用了也会犯错误，很多人再使用的时候有可能有以下的错误。第一系统变量没有设置好，这个要在我的电脑右键属性里面环境变量设置中的系统变量设置为Compxlib所在的目录，同时把vsim所在的目录也设置在里面。如果懒的设置也是可以有办法解决得。可以在－s后面用命令加上vsim所在的目录即可

  我从来都是这样弄的，从来没出现过不能使用的情况。

（2）从ISE 中编译库的问题（这个也非常好，但是这个只是针对你选择的器件编译，所以不如上面所列的详细）

     左边的工程窗口（source in project)，点中器件(在TOP层上面一级)，然后看下面的Processes for Source窗口 有Complie HDL Simulation Libraries，右键单击，有属性，设置完后双击运行就行了。但这样只是编译本器件相关的仿真库；

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