学习的过程就是不断debug的过程

今天在波形图中观察状态机时竟然发现编码不是我指定的方式，从新综合时仔细观察竟然也没有状态机自动编码的信息，网上搜了艘，可能是：我把状态机作为了输出信号，为什么这么说呢，看看帮助文档(the first one)就明白了。

The Quartus II software infers state machines for all registered, unsigned vector variables that satisfy the following conditions:

• The variable is not declared as a module output

• The values assigned to the variable are constant literals, parameters, enums (SystemVerilog), or other state variables.

• The variable has more than two states, in other words, it was assigned at least two distinct constant values.

• The variable is not indexed in an expression or referenced as an operand in an arithmetic expression. The latter condition prohibits state transition logic based on arithmetic relationship among the states, for example,next_state <= state + 1.

• The variable has at most one asynchronous reset condition

        一开始没有想到综合器对状态机识别问题，怀疑是软件有最大转态机数限制，没有抓住关键角度 。

        最后发现在tools ----netlist views----state machine viewer 可以显示所有所的状态机，当然是通过下拉选项选择，我的可以选择3个状态机，因为模块设计中设计了3个。

       昨天还发现了一个modelsim的秘密，开始问了很多人没有遇到过，也算是新发现吧。

       在modelsim中的信号宽度最多32 bits (64 bits ?,记性差的要命)，我的信号是190 bits,功能仿真时提示超过了最大值 32 bits !