用verlog实现8253的模式控制
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/************************************************************************
FMEw2W YN0?207219*************************************************************************EDA中国门户网站Bp#z1\tq+mw ~K
*************************************************************************EDA中国门户网站([i0WwR3YMHh
******** design project: channel 0 of 8253 timer ********
M(E6D5^K al
N207219******** designer : ********
efdAs7O5_!i#w207219******** company :sounthern yangtze university ********
/U#Wyk/`P H8J207219******** date : April 15th in 2007 ********
0s#I-h/S*q ?207219******** detail information: ********
P^*x\dh207219******** this module is the RTL description ********
2pI4sO:vnt207219******** of 8253 timer, it includes six operate ********
P3C[zD wP+_'Xp207219******** models ;the table following is the ********
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B?207219******** control words of channel 0 of 8253 timer: ********
&pg|9K&]+E m4L207219******** model0: 10H,11H, ********EDA中国门户网站yC4mI)@+b4L{YW-V
******** model1: 12H,13H, ********EDA中国门户网站[F(IK#}t
******** model2: 14H,15H, ********EDA中国门户网站_ |/i|k'jG$_G
******** model3: 16H,17H, ********EDA中国门户网站d.|"Q6I7Y
******** model4: 18H,19H, ********EDA中国门户网站?*Z&~7tT%e/v
******** model5: 1AH,1BH, ********
0imY"oh.b8cNc.H:M207219*************************************************************************EDA中国门户网站bc{7} U
*************************************************************************
BD%R^@)a6R207219*************************************************************************
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] wU cV#k2xNiN207219//
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W9}207219module TIME(out, // output of counter 0;
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Yacd207219 state_rd, // state of reading;
$P$X(x[p@G*C207219 d, // date of input;EDA中国门户网站
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d_out, // output of cuttently value;EDA中国门户网站S9W8[wEr%D
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gate, // control signal of gate ;EDA中国门户网站W$G e V3g!u5CybU7v
n_cs, // select signal;EDA中国门户网站WXj:f3r
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n_rd, // read signal;EDA中国门户网站d
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n_wr, // write signal;EDA中国门户网站`,g6G;yz]#sH!`
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a1, EDA中国门户网站*On9~\&I_i$P
a0,
9^0W'S'D;ki7MtI207219 clk); // clock signal;
+Y;dy;xA207219 // rst);EDA中国门户网站AY+I
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//
output [7:0] d_out;EDA中国门户网站3v`)A/lX
output out; EDA中国门户网站R0~Ae*UR*u
output state_rd;
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M V207219//
input gate,clk;
ju0W.?J/E207219input n_cs,n_wr,n_rd;
KJ9c9G1H8u-i207219input a1,a0; EDA中国门户网站DY(|3_
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input [7:0] d;EDA中国门户网站a$|7Cd t ?2[HM1O1W
//
reg [7:0] control; // reg of control word;
b0x4@4sd3I_-|207219reg [15:0] cnt,cnt1,cnt_a,cnt_b,cnt_c;
vPE(y*Z0x207219reg out_a;EDA中国门户网站%doI7ptQ0C)C
reg out_b;EDA中国门户网站y0W `\_t
reg start_f; // flag of startup;EDA中国门户网站2P{.T(Vv~i ~vy
reg state_wr; // state machine of writing;
9f'V2C.JY)^*JRPL+B207219reg state_rd; // state machine of reading;
ML?'UH)qh207219reg [1:0] cnt_f;EDA中国门户网站/] ~fPi
reg nta,fla,flb,flc,fld,sta;// some internal control signal;
B\1f0I7M'J3G207219//
wire [7:0] d_out;EDA中国门户网站6n$K!}
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wire nw_r;
VNBaB%qR207219wire ntb;EDA中国门户网站v*q0^] Oo6i
wire out;
m$yur`t6r"d-N/Mn207219wire clock;
L2}1D)cs9FT|4o A207219wire clock1;
//EDA中国门户网站` k9KCP4k
assign out=out_a && out_b;