DC Setup File:
# .synopsys_dc.setup
lappend search_path ../libs ./scripts ./unmapped
#set search_path “../libs ./scripts ./unmapped”
set target_library “core_slow.db”
set link_library “* core_slow.db”
set symbol_library “core.sdb”
alias h history
alias rc "report_constraint -all_violators"
Timing and Area Goals:
# constrain area
current_design CURRENT_DESIGN_NAME
set_max_area MAX_AREA_VALUE
# clock setup
create_clock -period PERIOD [get_ports Clk]; # find(port, CLK*)
set_dont_touch_network [get_clocks Clk]; # find(clock, sysclk)
set_clock_uncertainty VALUE [get_clocks CLK]
#set_clock_latency -source VALUE CLK
#set_propagated_clock CLK
# input/output timing
set_input_delay -max 4 -clock Clk [get_ports A]; # $all_ins_except_clk
#remove_input_delay [get_ports CLK]
set_output_delay -max 5.4 -clock Clk [get_ports B]; # [all_outputs]
Environmental Attributes:
# environment attributes
report_lib libname :list the vendor-supplied operating conditions
set_operating_conditions –max <operating_condition>
set_operating_conditions -max slow_125_1.62
#set_min_library core_slow.db -min_version core_fast.db
set_operating_conditions -max slow_125_1.62 -min fast_0_1.98
# load
set_load 5 [get_nets CLK]
set_load 5 [get_ports OUT1]
set_load [load_of my_lib/and2a0/A] [get_ports OUT1]
set_load [expr [load_of my_lib/inv1a0/A] * 3] OUT1
# driving cell
set_driving_cell –lib_cell <cellname> -pin <pin name> <port list>
set_driving_cell -lib_cell and2a0 [get_ports IN1]; # [all_inputs]
remove_driving_cell [get_ports Clk]
# WLM
report_lib libname
set_wire_load_model -name 160KGATES
set auto_wire_load_selection false :Turn off automatic wire load model selection
Design Rules:
# Limit the input load
set_max_capacitance <max_load> <port list>
set MAX_INPUT_LOAD [expr [load_of tech_lib/and2a0/A] * 10]
set_max_capacitance $MAX_INPUT_LOAD [all_inputs]; # $all_ins_except_clk
#remove_attribute [get_ports Clk] max_capacitance
# Model the max possible load on the outputs, assuming
# outputs will only be tied to 3 subsequent blocks
set_load [expr $MAX_INPUT_LOAD * 3] [all_outputs]
Reports:
# report
report_port -verbose :Returns all attributes and constraints placed on all input and output ports (report_port -v Clk)
report_clock :Returns the source, waveform. and period of all clock objects in current_design
report_timing
report_constraint -all_violators
report_lib lib_name > reports/core_slow.rpt
report_compile_options :will tell you the status of the flatten and structure attributes on the current_design
Compile:
# compile design
compile –inc –only_design_rule
compile -map_effort (low | medium | high)
compile -incremental_mapping
compile -inc -map high
