Lattice Adds Block Modular Design to ispLEVER FPGA Design Tools
- Includes Support for New MachXO Programmable Family -
HILLSBORO, OR - JULY 18, 2005 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of its ispLEVER® 5.0 Service Pack 1 (SP1) update for its programmable logic design tool suite. With this update, the design tool suite now supports a Block Modular Design flow that provides productivity-enhancing Incremental Design capability. The Service Pack 1 update also enhances the functionality and performance of the tool suite for DSP design. In addition, initial design support for the new Lattice MachXO™ Crossover Programmable Logic devices also is included. Substantial improvements in design frequency, logic utilization and compilation time further improve the exceptional performance of the ispLEVER software.
Lattice vice president of software Chris Fanning said, "With the productivity improvements delivered by Block Modular Design, performance enhancements such as distributed RAM-based shift registers, loadable counters, and LUT-based multipliers, and the addition of design support for our new MachXO family, ispLEVER design software delivers extraordinary value to our customers."
"ispLEVER design support for MachXO devices means our customers can now access the device family's combination of innovative non-volatile embedded Flash plus SRAM technology, embedded block RAM, Lattice's unique TransFR™ capability for in-field logic updates and extremely low standby power using our new Sleep Mode," said Stan Kopec, Lattice vice president of corporate marketing. "And, we're delivering all these capabilities and features at up to a 50% lower cost per logic function."
Improved ispLEVER Support for Team and Incremental Design Methods
The ispLEVER 5.0 SP1 software includes improvements that reduce the time and effort required to implement a large FPGA design. The new Block Modular Design (BMD) flow allows a design team to collaborate on a design in parallel, or may be employed as part of an incremental design strategy that is especially effective when isolated changes to a design are required.
BMD allows distributed teams to fully implement one or more block modules through place and route in parallel. Before BMD, only the logic synthesis design phase could practically be performed in parallel. BMD enables a system engineer to budget resources, floor plan, and set timing objectives for one or more design block modules based on the hierarchy and interconnect of a top-level structural model. Anchor points and regions of each block module are defined in a new GUI application called the Block Module Wizard. Each block module can then be implemented by one team member in parallel with the others. The system provides utilization feedback to the designer based on the budget and allows each design module to be placed and routed to completion independently. A final assembly phase merges each design module with the whole design while retaining the placement and timing characteristics of each completed block module.
SP1 includes new BMD-related online help topics and a tutorial. BMD-related features are compatible with LatticeEC™, LatticeECP™ and LatticeXP™ FPGAs, as well as the MachXO devices.
Robust Functionality and New Features
ispLEVER 5.0 Service Pack 1 delivers a host of new capabilities that enhance design productivity. New capabilities that support FPGA design include distributed RAM-based shift registers, loadable counters, and LUT-based multipliers. New versions of Mentor Graphics' Precision RTL and Synplicity's Synplify synthesis tools also are included and boost silicon performance to record levels.
DSP design enhancements to the ispLeverDSP flow have been made, greatly increasing the performance and usability of the tool. Features added or enhanced include:
Improved hierarchical subsystem support, easily allowing the designer to easily break large, complex designs into smaller, reusable, more manageable blocks instantiated as subsystems.
Support for external library links, enabling users to develop their own set of blocks for design reuse.
Support for distributed ROM as well as EBR ROM.
Support for M channel, N tap, X multiplier FIR filter designs that adds to ease-of-use and achieves new performance levels.
Carry In/Out support for AddSub Block for increased performance.
Improved simulation and compilation times.
A complete list of new ispLEVER 5.0 Service Pack 1 features and enhancements can be viewed athttp://www.latticesemi.com/produ ... ispLEVER-50sp1.cfm.
Starter
In addition to supporting the MachXO family, the downloadable ispLEVER-Starter configuration will be expanded in August to include support for the LatticeXP3 and LatticeXP6 devices. The ispLEVER-Starter software will support the devices mentioned above as well as the entire LatticeEC family, the LatticeECP6 device, and all Lattice CPLD, ispGDX2™ and SPLD devices. No other downloadable programmable logic software design tool is as comprehensive.
Availability
The ispLEVER 5.0 Service Pack 1 for Windows, UNIX, and LINUX operating systems is available for download immediately from the Lattice Semiconductor Corporation web site athttp://www.latticesemi.com/products/devtools/software/index.cfmor through the Lattice's ispUPDATE facility. SP1 requires ispLEVER 5.0, which is available for purchase through Lattice representatives or online at:http://www.latticesemi.com/store/software.cfm.
