关于if的综合结果,很奇怪

关于if的综合结果,很奇怪写了两个测试电路测试结果:
1.对DC来说无区别,看来DC的优化能力真强大
2.用quartus来综合,分开写反而好,有兴趣的可以试试.

module test_if(clk,rst,out);
input clk, rst;
output out;
reg[5:0] cnt;
reg out;
[email=always@(posedge]always@(posedge[/email] clk or negedge rst)
if(!rst)begin
cnt<=6'b000000;
out<=1'b0;
end
else if(cnt<54) begin
cnt<=cnt+6'b1;
out<=1'b1;
end
else if(cnt>=59)begin
cnt<=cnt+6'b1;
out<=1'b1;
end
else if(cnt==55)begin
cnt<=cnt+6'b1;
out<=1'b1;
end
else if(cnt==57)begin
cnt<=cnt+6'b1;
out<=1'b1;
end
else begin
cnt<=6'b000000;
out<=1'b0;
end
endmodule

module test_if_2(clk,rst,out);
input clk, rst;
output out;
reg[5:0] cnt;
reg out;
[email=always@(posedge]always@(posedge[/email] clk or negedge rst)
if(!rst)begin
cnt<=6'b000000;
out<=1'b0;
end
else if(cnt<54 || cnt>=59 || cnt==55 || cnt==57 ) begin
cnt<=cnt+6'b1;
out<=1'b1;
end
else begin
cnt<=6'b000000;
out<=1'b0;
end
endmodule

test_if.JPG

test_if_2.jpg