How Verilog PLI works

• Write the functions in C/C++ code.
• Compile them to generate shared libs (*.DLL in Windows and *.so in UNIX). Simulator like VCS allows static linking.
• Use these Functions in Verilog code (Mostly Verilog Testbench).
• Based on simulator, pass the C/C++ function details to simulator during compile process of Verilog Code (This is called linking, and you need to refer to the simulator user guide to understand how this is done).
• Once linked just run the simulator like any other Verilog simulation.

During execution of the Verilog code by the simulator, whenever the simulator encounters user defined system tasks (the ones which start with $), the execution control is passed to the PLI routine (C/C++ function).

注：Once linking is done, simulation is run as a normal simulation as we saw earlier, with slight modification to the command line options: we need to tell the simulator that we are using PLI (Modelsim needs to know which shared objects to load in the command line).

具体的可以参见以下网址：

verilog PLI介绍