请教高手The DDIO_OUT WYSIWYG primitive。。。

请教高手The DDIO_OUT WYSIWYG primitive。。。I am trying to compile a design in Quarus II 8.0sp1 beta with the following components:
- Nios CPU
- JTAG
- Onchip memory
- DDR SDRAM High performance controller
- timer

I keep getting this error and I cannot figure out how to fix it:

Error: The DDIO_OUT WYSIWYG primitive "ddr_design:inst|ddr:the_ddr|ddr_controller_phy:ddr _controller_phy_inst|ddr_phy:alt_mem_phy_inst|ddr_ phy_alt_mem_phy_ciii:ddr_phy_alt_mem_phy_ciii_inst |ddr_phy_alt_mem_phy_clk_reset_ciii:clk|altddio_bi dirDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_cmg:auto_generated|ddio_ outa[0]" feeding the pin "ddr_mem_clk[0]" has multiple fan-outs

If I double click on the error then I get to this line:

ddio_outa[0..0] : cycloneiii_ddio_out
WITH (
async_mode = "none",
power_up = "low",
sync_mode = "none",
use_new_clocking_model = "true"
);

in the file

db/ddio_bidir_cmg.tdf

Any ideas?

Thanks