clock divider

module clk_divEDA中国门户网站I0]
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 input iclk,EDA中国门户网站"h{IF-}%G W3O3_-_
 output reg oclk
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parameter clk_reg_length=5;EDA中国门户网站P.m]E!z6o\
`define length clk_reg_length

reg [`length-1:0] clk_reg;

always@(posedge iclk)
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  clk_reg<=clk_reg + `length-1'b1;EDA中国门户网站J-\FR#h!O F"m
  oclk<=clk_reg[`length-1];  EDA中国门户网站0_-|1KT"B+DH2B
 end
A:M:E`Ar^8nK88381endmodule