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SOC验证 大家都用什么语言
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Nicran发布于2006-02-23 13:08:22
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OpenVera -> SystemVerilog
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luxboy2000发布于2006-02-23 14:53:43
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哪些公司在用SystemC做验证?
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verif_expert发布于2006-02-24 09:45:15
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Currently, there are following types of languages:
Specman or e
Vera
SystemC
SystemVerilog
The order respects to their adoption time. Let me give a short description on all of them: Specman is invented by Verisity. It is a LISP style language. Compared with that, Vera is a C/Verilog style language. In early 2000, Specman is widely used due to its powerful randomization technology. However, Vera catches up. Currently, Vera and Specman each has 50% of US testbench market.
SystemC has been around for many years. It originally used in Intel to model performance and design. However, when Verilog catches up, most designers like to use Vera/Specman because they are more hardware-like. It is nothing but habit. That is why SystemC was abandoned by many companies. However, SystemC is revived because of SOC. Many companies like to model HW/SW at the same platform. SystemC is apparently better choice for that purpose. I know many wireless companies use SystemC as the verification language.
SystemVerilog is the direct deviation of Vera and Verilog. That is definitely the furture. It solves the fundamental multi-language issues in simulation. Why multi-language is an issue? I leave that to you to think. On the other hand, SVA captures the assertions trend as well. To be honest, SVA is pretty sucky. PSL is much better semantically. However, that is the reality. PSL is not in System Verilog.
If you start to learn verification language, I suggest that you directly jump to SystemVerilog. VCS/NCSIM all supports SystemVerilog now. I believe Mentor also announce their support to SV recently.
A few more points regarding to Vera:
1. Vera has a very powerful constraint solver to solve the randomization problems. Please note that that is fundamentally very difficult problem: NP-hard. That gave Vera a lot of edge over other tools. I don't know how well Specman's constraint solver.
2. e is a pretty language. I have played with it before. The problem is that it is not a standard. I believe Cadence is pushing it to standard. But it is too late. SystemVerilog has comed up.
3. If you are interested in formal verification, I mean functional formal verification, you should really look at SVA, PSL or OVL. Don't look at OVA. That is really really bad.
Sorry, I cannot write Chinese fast. Hopefully, English is ok.
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kevin8228
发布于2006-02-24 14:08:46
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To verif_expert :
谢谢你的建议,SystemVerilog 的工具非常少 VCS/NCSIM 最新版本支持SystemVerilog ? 我们实验室的版本好像不行
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hfly47发布于2006-02-28 16:23:37
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我们实验室用的是SystemC，其它的没用过
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hent_yang发布于2006-02-28 22:04:26
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如果money少，就用vera，现在vera反正已经集成到vcs中了，vera相对systemc更适合验证
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visualart发布于2006-03-17 21:18:24
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e language
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longgangtou发布于2006-03-19 14:10:14
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现在正在开始用synopsys vera做，但是找不到相关的材料！
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pinglet发布于2006-04-06 17:53:02
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SystemC用在什么样的软件环境中呢？目前EDA软件公司都支持吗？
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wwwzp
发布于2006-04-06 18:29:09
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SystemVerilog应该有前景
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yyh3515发布于2006-04-10 10:01:39
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VERA加SYNOPSYS的RVM个人感觉很适合SOC和可重用的验证.
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guagua发布于2006-04-21 15:02:51
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ding~
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daryl发布于2006-04-21 15:41:21
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both, both
