关于毕业设计数字频率计

  终于快毕业了，毕业设计的题目是基于CPLD/FPGA的数字频率计，测频范围是0。1～10M赫兹，要能实现自动转换测频测周。说白了，就是要用状态机进行主控制状态转移，所以我把整个设计分成了以下几个模块：状态机、计数器、分频器、同步整形电路、锁存器、时钟选择器、七段数码管显示程序。用自顶向下的方法进行设计，把每个模块的程序设计好。不过现在遇到些问题，所以想向高手请教一番，下面是我设计的状态机的程序，仿真通过没有问题，但是我不知道这样的写法等下载到芯片上能不能实现到转移状态，因为我现在还没有芯片，不能实际操作，请高手指点指点。

library ieee;
use ieee.std_logic_1164.all;
entity statemachine is
port
(clock:in std_logic;
 clock01hz,clock1hz,clock10hz,clock100hz,clock1khz,clock10khz,clock100khz,clock1mhz,clock10mhz:in std_logic;
 low,over:in std_logic;--欠量程与过量程信号
 reset:in std_logic;
 en:out std_logic; --控制七段数码管的显示
 dp1,dp2:out std_logic;--百位小数点与十位小数点
 overlight,lowlight:out std_logic;--超量程指示灯
 period:out std_logic;--指示测频、测周状态，1为测周
 outclock:out std_logic);--输出时基信号
end;
architecture mooremachine of statemachine is
type state_type is(f100m,f10m,f1m,f100k,f10k,p1ms,p10ms,p100ms,p1s,p10s,overflowh,overflowl);
signal state:state_type;
begin
process(clock10mhz,reset)
begin
if (reset='1')then
state<=f100k;
elsif rising_edge(clock10mhz)then
case state is
when f100m=> if over='1' then
state<=overflowh;
elsif low='1' then
state<=f10m;
else state<=f100m;
end if;
when f10m=> if over='1' then
state<=f100m;
elsif low='1' then
state<=f1m;
else state<=f10m;
end if;
when f1m=> if over='1' then
state<=f10m;
elsif low='1' then
state<=f100k;
else state<=f1m;
end if;
when f100k=> if over='1' then
state<=f1m;
elsif low='1' then
state<=f10k;
else state<=f100k;
end if;
when f10k=> if over='1' then
state<=f100k;
elsif low='1' then
state<=p1ms;
else state<=f10k;
end if;
when p1ms=> if over='1' then
state<=p10ms;
elsif low='1' then
state<=f10k;
else state<=p1ms;
end if;
when p10ms=> if over='1' then
state<=p1ms;
elsif low='1' then
state<=p10ms;
else state<=p10ms;
end if;
when p100ms=> if over='1' then
state<=p1s;
elsif low='1' then
state<=p10ms;
else state<=p100ms;
end if;
when p1s=> if over='1' then
state<=p10s;
elsif low='1' then
state<=p100ms;
else state<=p1s;
end if;
when p10s=> if over='1' then
state<=overflowl;
elsif low='1' then
state<=p1s;
else state<=p10s;
end if;
when overflowh=> if low='1' then
state<=f10m;
elsif over='1' then
state<=overflowh;
else state<=f100m;
end if;
when overflowl=> if low='1' then
state<=p1s;
elsif over='1' then
state<=overflowl;
else state<=p10s;
end if;
end case;
end if;
end process;

process(state)
begin
case state is
when f100m=>
en<='1';--允许七段数码管显示数字
outclock<=clock1khz;--时基信号为1khz
overlight<='0';--待测信号频率未超过总量程
lowlight<='0';
period<='0';--表示系统处于测频状态
dp1<='0';--百位小数点不亮
dp2<='0';--十位小数点不亮
when f10m=>
en<='1';
outclock<=clock100hz;
overlight<='0';
lowlight<='0';
period<='0';
dp1<='0';
dp2<='0';
when f1m=>
en<='1';
outclock<=clock10hz;
overlight<='0';
lowlight<='0';
period<='0';
dp1<='0';
dp2<='0';
when f100k=>
en<='1';
outclock<=clock1hz;
overlight<='0';
lowlight<='0';
period<='0';
dp1<='0';
dp2<='1';
when f10k=>
en<='1';
outclock<=clock01hz;
overlight<='0';
lowlight<='0';
period<='0';
dp1<='0';
dp2<='1';
when p1ms=>
en<='1';
outclock<=clock10mhz;
overlight<='0';
lowlight<='0';
period<='1';
dp1<='1';
dp2<='0';
when p10ms=>
en<='1';
outclock<=clock1mhz;
overlight<='0';
lowlight<='0';
period<='1';
dp1<='0';
dp2<='1';
when p100ms=>
en<='1';
outclock<=clock100khz;
overlight<='0';
lowlight<='0';
period<='1';
dp1<='0';
dp2<='0';
when p1s=>
en<='1';
outclock<=clock10khz;
overlight<='0';
lowlight<='0';
period<='1';
dp1<='0';
dp2<='0';
when p10s=>
en<='1';
outclock<=clock1khz;
overlight<='0';
lowlight<='0';
period<='1';
dp1<='0';
dp2<='0';
when overflowh=>
en<='0';
outclock<=clock1khz;
overlight<='1';
lowlight<='0';
period<='0';
when overflowl=>
en<='0';
outclock<=clock1khz;
overlight<='0';
lowlight<='1';
period<='1';
end case;
end process;
end;

以上便是状态机的程序，望各位高手不要吝啬，多指点一下我这个对VHDL语言有强烈兴趣的应届毕业生