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Transistor Geometry in Substrate Diodes
上一篇 / 下一篇 2008-05-05 15:56:03 / 个人分类：技术专区
Transistor Geometry in Substrate Diodes
The substrate diode is connected to either the collector or the base depending on whether the transistor has a lateral or vertical geometry. Lateral geometry is implied when the model parameter SUBS=-1, and vertical geometry when SUBS=+1. The lateral transistor substrate diode is connected to the internal base and the vertical transistor substrate diode is connected to the internal collector. Figure 28 and Figure 29 show vertical and lateral transistor geometries.
Figure 28 Vertical Transistor (SUBS =+1)
Figure 29 Lateral Transistor (SUBS =-1)
In Figure 30, the views from the top demonstrate how IBE is multiplied by either base area, AREAB or collector area, AREAC.
Figure 30 Base, AREAB, Collector, AREAC
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