Security Blanket & Logic Lockdown

The most common theft mechanism hitting systems designer today is Overbuilding. Generally, there are two ways to steal the design, reverse engineering, and cloning. In American law, reverse engineering is allowed for some reason. So reverse engineering consulting company have a lot of customers, who have two minds: semiconductor companies want to know how their competitors’ products work and legal professionals want to prove that their clients’ patents were infringed or that their devices were copied in their entirety.

There are different ways to avoid the thieves in ASIC and FPGA. In ASIC, reversing engineering is popular in ASIC. But if you have an ASIC with 90ns ASIC with 10 layers of metal and billion transistors, reverse engineering is non-sense.

As a Manager, the MOST important decision is regarding how and ho much to protect your design is economic.

In FPGA area, the story is complicated. The configuration file of SRAM-based FPGA (Xilinx and Altera) is stored in the external PROM, which is easy to steal and re-generated to design file. The most common way of anti-theft is encryption. The bitstream Is encrypted, and an encryption key programmed into the FPGA device itself. Only an FPGA encoded with the correct encryption key can read the encrypted bitstream. Xilinx and altera have different mechanism to encrypt. (Check the second articles). Now, there are other type of FPGA which use more safe way to protect the design. For instance, antifuse FPGAs from actel and Quicklogic, and Flash FPGAS from Actel and Lattice and Altera’s Max II CPLD.