我的验证经验
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下一篇 2006-07-18 13:53:15 / 天气: 晴朗
/ 心情: 高兴
/ 个人分类：思考
今天都是以前一些在另一个blog上的文章，决定把他们都搬到这边来。
- In self-checking, how to make the stim and ref. dataset smartly is
very important. Good stim and ref can save you a lot of precious time.
- Careful,
do not waste time because a stupid typo. It is very difficult to find a
typo sometimes, because you do not know where is the "tiny" typo.
- In self-checking, the difficulty is how to do some specific thing at a specific time.
- I found the state-of-art methodology
of ASIC can not satisfy myself. It is awkwurd. Some time I have to
check the waveform to make sure the timing is correct. As I know, there
are some assertion language can do something to ease the
verificationer's labour. But ask all the tester especially most of test
is ASIC designer to master some special language is not a easy thing.
The simpler language the better. In my mind, on block level
verification, some HDL language (Systemverilog, VHDL 200x, systemC?
)plus assertion language is better, becasue verilog and VHDL is familar
with designers, and SystemC is based on C++, maybe not hard to master.
In high level, some high abstracted language can be used. Of course the
problem is the interface between toplevel and block level, and another
important is synthesizebility of in toplevel. Because the simulation
may run on the emulator, so the toplevel testbench sometimes ask
synthesizeable. This is a question that HDL language still have its
place nowadays. Develop a perfect methedology and language, free the
testers from the waveform is urgent. I believe, sooner later, the test
only need run testcase, use scripts to find the error rather than
search the waveform.
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