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VHDL.Verilog实现有符号数乘法（转载）

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VHDL.Verilog实现有符号数乘法

在数字信号处理（DSP）中，乘加是最基本的运算，以至于很多FPGA厂商以MAC的多少及运算速度做为器件的一个重要指标。下面就乘法实现进行讨论。
在DSP中，大多是有符合数的操作，这里给出有符号数乘法的VHDL和Verilog程序。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY signed_mult IS
PORT (clk: IN STD_LOGIC;
a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END signed_mult;

ARCHITECTURE rtl OF signed_mult IS
SIGNAL a_int, b_int: SIGNED (7 downto 0);
SIGNAL pdt_int: SIGNED (15 downto 0);
BEGIN
result <= STD_LOGIC_VECTOR(pdt_int);
Process(clk)
Begin
If rising_edge(clk) then

a_int <= SIGNED (a);
b_int <= SIGNED (b);
pdt_int <= a_int * b_int;
end if;
end process
END rtl;
相应的Verilog程序：
module signed_mult (out, clk, a, b)
output [15:0] out;
input clk;
input signed [7:0] a;
input signed [7:0] b;
reg signed [7:0] a_reg;
reg signed [7:0] b_reg;
reg signed [15:0] out;
wire signed [15:0] mult_out;
assign mult_out = a_reg * b_reg;
always@(posedge clk)
begin
a_reg <= a;
b_reg <= b;
out <= mult_out;
end
对于无符号数，只需要将其中的signed换成unsigned即可。