FPGA debugger works at full speed

By Christoph Hammerschmidt Courtesy of EE Times EuropeEDA中国门户网站n2izGe9M#u.e
uV

MUNICH, Germany — EDA startup EDAptability has announced the availability of its FPGA and ASIC debugging tool TotalScope. With a combination of RTL level elaboration, model extraction and modification techniques with simulation, the tool offers unrivaled signal visibility, the company claims.

The tool offers debugging at speed which means that the process runs at full clock speed, explained Tobias Strauch, founder and CEO of EDAptability. No re-synthesis is needed for debugging; the general debug structure initially implemented has no impact on timing or on the combinatorial logic, claimed Strauch.

The software offers 100 percent RTL signal visibility, Strauch claims. The signals with their original names and types can be viewed with the company's VCD viewer software as well as with any third-party VCD viewer.

The product can run on standard Altera or Xilinx cables without the need for additional or external hardware, the company said. As an option, the program can run on EDAptability's SPE hardware.