三分频复习

先用状态机实现占空比1：2的

module div_fsm (clk,rst,div3);
input                clk,rst;
output                div3;
reg                div3;

parameter[1:0]  S0=2'd0,
                S1=2'd1,
                S2=2'd2;

reg[1:0]                state,next_state;

always @ (posedge clk)
begin
        if(!rst) state<=S0;
        else     state<=next_state;
end

always @ (state)
begin
        //default values
        next_state=S0;
        case (state)
                S0: begin
                         next_state=S1;
                         div3=0;
                    end
                   
                S1: begin
                         next_state=S2;
                         div3=0;
                    end
                            
                S2: begin
                         next_state=S0;
                         div3=1;
                    end
                   
                        endcase
end
endmodule

module div_fsm_t;
reg         clk,rst;
wire        div3;

div_fsm U1(clk,rst,div3);

initial begin
        clk=0; rst=0;
        #300   rst=1;
end

always #50 clk=~clk;
endmodule
再贴一个占空比1：1的

module three(reset,clk,clk3);
input clk,reset;
output clk3;
reg a,b;
wire d,e,f,clk3;
assign d=(~a)&(~b);
assign e=clk|~b;
assign f=a|clk3;
assign clk3=e&f;
always @(posedge clk or negedge reset)
begin
if(~reset)
        a<=0;
else
a<=d;
end
always @(posedge clk or negedge reset)
begin
if(~reset)
b<=0;
else
b<=a;
end
endmodule

module test_beach;
reg clk;
reg reset;

wire clk3;
three three1(reset,clk,clk3);
always #5 clk=~clk;
initial begin
$monitor($time,,"clk=%b,clk3=%b",clk,clk3);
#5 reset=0;
#5 reset=1;
#10 clk=0;
#300 $finish;
end
endmodule

好好研习一下，加油