MIG1.6的使用

      这里要解释一下为什么我原来的mig安装后不能用，根据xilinx文档，要想使用mig1.6，ise8.1需要打个补丁ise_81i_ip_update1之外，还需要一个安装文件 8_1_03i_win，我当时是因为某些原因，缺少了后者，所以一直没能使用mig生成DDR控制器。

        这里简单介绍一下mig1.6：

       The Memory Interface Generator (MIG) 1.6 tool generates DDRII SRAM, DDR SDRAM,DDR2 SDRAM, QDRII SRAM, and RLDRAM II interfaces for Virtex™-4 FPGAs and generates DDR2 SDRAM and QDRII SRAM interfaces for Virtex-5 FPGAs. It also generates DDR and DDR2 SDRAM interfaces for Spartan™-3 FPGAs and DDR SDRAM interfaces for Spartan-3E FPGAs. The tool takes inputs such as the memory interface type, FPGA family, FPGA devices,frequencies, data width, memory mode register values, and so forth,from the user through a graphical user interface (GUI). The tool generates RTL, SDC, UCF,and document files as output. RTL or EDIF (EDIF is created after running a script. file,where the script. file is a tool output) files can be integrated with other design files.

       这里先介绍一下如何使用mig1.6，然后再介绍如何使用mig1.6生成的DDR控制器。

Using the MIG 1.6 Tool

       The MIG 1.6 tool is used to generate memory interfaces for Xilinx FPGAs. The tool generates either Verilog or VHDL RTL design files, UCF and script. files that run synthesis, and PAR files for the selected FPGA and the selected memory interface.

        这里要说明一下，这个控制器的UCF文件是不可修改的，我在布局布线时曾尝试着挪动它内部的部分器件，因为它妨碍了我工程内部其他模块的器件摆放。结果修改后布局却仍是原来的样子。

       上图中红线圈出的部分可进行xilinx器件选择，DDR型号选择，以及初始化时涉及的相关参数的设置。这里还是需要对DDR的工作模式有一定的了解才能设置出合适的参数。图片中部的红圈里可以输入最后生成的控制器的名字，DDR的并行数据位，根据器件的实际参数来设置。除此之外还可以选择FPGA内用到的bank和管脚并自动生成UCF文件，最后生成的控制器可以是VHDL或者verilog的，并且会生成一个自带用户模块的直接用来仿真，同时生成一个独立的控制器，与外部用户模块需要自己做接口。生成的代码功能完整，是一个很好的例程，有兴趣可以去深入分析，为自己以后写模块有很大的帮助哦！由于是xilinx公司提供的，所以它充分利用了xilinx的FPGA内部资源，库单元的使用是菜鸟学习的榜样。这里还要提一句，这个mig生成的控制器模块不能够做后仿真。

        下面按照上一篇的顺序介绍一下该DDRController的内部结构和使用：

        它内部完全实现了下图所示的状态转换，用户在使用时不需关心这些，只要会利用它的输入输出引脚按照要求输入命令和数据就可以了。

模块划分：

下面就各模块实现作简单介绍：

1、Controller
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tW0The DDR SDRAM controller initializes the memory, accepts and decodes user commands,and generates READ, WRITE, and REFRESH commands. The DDR SDRAM controller also generates signals for other modules. The memory is initialized and powered-up using a defined process. The controller state machine handles the initialization process upon power-up. If the AUTO REFRESH command is to be issued between any user read or write commands, then the read or write command will be suspended until the ref_done flag is deasserted.

2、Datapath
m!iJ2T"@'?-Qxl@0This module transmits data to the memories. Its major functions include storing the write data and calculating the tap value for the read datapath. The data_write and data_path_IOBs modules do the actual write functions. The Idelay_ctrl, tap_ctrl and data_tap_inc modules do the calibration.EDA中国门户网站aw-b6VL+M5\W/eVv

3、User InterfaceEDA中国门户网站&z3SIDXjA7E
This module stores write data in its Write Data FIFO (wr_data_fifo), stores write and read addresses in its Read/Write Address FIFO (rd_wr_addr_fifo), and stores received read data from memory in its Read Data FIFO (rd_data_fifo). The width of the Write Data FIFO is twice the data width and mask width of the memory. For example, for a 16-bit width, the width of the FIFO is 36 because the data width is 32 and the mask width is 4. The rd_wr_addr_fifo and wr_data_fifo modules store the data and address in block RAMs. The rd_data_fifo module captures the data in the LUT-based RAMs.EDA中国门户网站R&E.T.{n Hfs
The controller also generates user commands, such as READ and WRITE.EDA中国门户网站[4@0kxb"Sl[!wD y
The pattern_compare module registers the delay between the command and the data received from the IOBs. This delay is then applied to the Rden signal generated from the ddr_controller module during the actual read to register the valid data in the internal FIFOs.
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4、Infrastructure
)Wh{3I&K;s%L;\0The infrastructure module generates the FPGA clocks and reset signals. A DCM generates the phase-shifted clocks (clk0, clk90), refresh clock, and calibration clock. All the reset signals required for the design are also generated.

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5、IOBS Module
$fmm4?&A9E(]g*R0All DDR SDRAM address, control, and data signals are transmitted and received in the through the input and output buffers.

DDRController控制引脚功能说明：

DDR SDRAM Writes (User Interface)：

the timing diagram for a user write burst to the DDR SDRAM with burst lengths set to four. The user interface signals consist of WDF_ALMOST_FULL, APP_AF_WREN, APP_AF_ADDR, APP_WDF_WREN, and APP_WDF_DATA. The user interface consists of a Write Address FIFO and a Write Data FIFO for memory write operations.EDA中国门户网站)O$CT*D?K2^
The user initiates a write to memory by writing to the User Write Data FIFO and User Write Address FIFO when WDF_ALMOST_FULL or AF_ALMOST_FULL is deasserted. The ALMOST_FULL signals are asserted when the FIFOs are almost full; their offset values are specified in the design. The APP_AF_WREN signal is the write-enable signal for the Address FIFO, and APP_AF_ADDR is the write address to the Write FIFO. The APP_WDF_WREN signal is the write-enable signal for the Write Data FIFO, and APP_WDF_DATA is the user write data to the memory. APP_WDF_DATA is twice the width of the memory width, consisting of rising-edge and falling-edge data. The controller starts reading and decoding the Address FIFO when the empty signal is deasserted. It generates the command to the memory and other control signals based on the CAS latency and the burst length.EDA中国门户网站L.gi y(\)\2X7Wz
For burst lengths of four, each write address consists of two write data cycles. Figure shows a write burst with four consecutive bursts. In Figure 2-5, APP_AF_WREN is issued as per the test bench given with the MIG tool generated design. Users can issue APP_AF_WREN continuously irrespective of the burst length.

DDR SDRAM Reads (User Interface)：

the timing diagram for a user read burst with burst length set to four. The user interface signals consist of AF_ALMOST_FULL, APP_AF_WREN, APP_AF_ADDR,READ_DATA_VALID, and READ_DATA_FIFO_OUT.EDA中国门户网站*u:L"}\W `.b!n`
To initiate a memory read, the user writes the read address to the Read Address FIFO when the AF_ALMOST_FULL signal is deasserted (not full). The APP_AF_WREN signal is the write-enable signal for the Read Address FIFO, and APP_AF_ADDR is the memory read address. The read_data_valid signal is asserted when the read data is available to the user, and READ_DATA_FIFO_OUT is the read data from the memory to the user.EDA中国门户网站 Wc#m2@EI2Ja bf:t#r
Consequently, the controller generates signals based on the CAS latency and the burst length. Prior to the actual read and write commands, the design calibrates the latency between the read command issued and the data received in terms of number of clock cycles, using a pattern_compare8 module per bank. This clock count is used to delay the ctrl_rden signal and generate READ_EN_DELAYED_RISE and FIFOs. So a valid data is registered in the Read Data FIFO.
]%L-\6OV5LG0The MIG tool ensures that a DQS and its corresponding DQ signals do not cross a bank boundary.
5sn8DR k6G0Figure  shows the read latency. For BL = 4 and CL = 3, the read latency is calculated from the point when the read command is given by the user to the point when the data is available with the READ_DATA_VALID signal. It is assumed that the user issues the commands after initialization is complete and that the first command issued is a read command to row address 0.

最后要提一下，因为这个模块不能在modulesim里进行布局布线后仿真，所以要想检测它工作是否正常，只有把它生成的.bit文件下载到板子上进行测试，可以利用板上的GPIO连接的LED做检测，但是这是在数据量少的时候。当我要控制DDR读写大量数据进行测试时，必须利用Chipscop读出实时数据来进一步测试，通过后才可应用于系统中。

这是mig1.6生成的DDRController在我的系统中应用的RTL图：

DDRController模块内部结构：

其中的Idelay_ctrl0模块内部如下：

这个idelayctrl0模块是对xilinx器件库里的idelayctrl的例化，这个单元的使用使DDR控制器在高频率下保持稳定工作，使DQ和DQS之间严格的是需要求得到满足。以后会对这个做进一步介绍。

top_00模块内部结构：